The goal of this project was the integration of new-generation reprogrammable, read-only memory devices (both EPROM and EEPROM) for the application-specific IC (ASIC) market into:
- one-micron and low-voltage (1.5 V, 2 micron design rule) CMOS (in the first phase of the project)
- 0.8 micron and low-voltage (1.5 V, 1.5 micron design rule) CMOS (in the second phase).
At the start of the project the availability of cell libraries and CAD tools for non-volatile memory was quite limited. One of the main objectives of the project has thus been the development of cell libraries for EPROM and EEPROM blocks and distributed memory, together with all the support circuitry, such as decoders, sense amplifiers, high voltage generators, etc. CAD tools to design and correctly match memory blocks of arbitrary size had also to be developed, as well as routing tools to handle the special high voltage requirements.
20041 Agrate Brianza Milano