Computation-in-memory architecture based on resistive devices

Información del proyecto

MNEMOSENE

Identificador del acuerdo de subvención: 780215

DOI

10.3030/780215

Proyecto cerrado

Fecha de la firma de la CE 31 Octubre 2017

Fecha de inicio 1 Enero 2018

Fecha de finalización 30 Junio 2021

Financiado con arreglo a

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coste total

€ 3 998 120,00

Aportación de la UE

€ 3 998 120,00

Coordinado por

TECHNISCHE UNIVERSITEIT DELFT
Netherlands

CORDIS proporciona enlaces a los documentos públicos y las publicaciones de los proyectos de los programas marco HORIZONTE.

Los enlaces a los documentos y las publicaciones de los proyectos del Séptimo Programa Marco, así como los enlaces a algunos tipos de resultados específicos, como conjuntos de datos y «software», se obtienen dinámicamente de OpenAIRE .

Resultado final

Documents, reports (17)

Refined CIM architecture

Final ISA specification of the whole CIM architecture including the instruction set simulator.

Report on mapping of micro-kernels to macro-architecture

This report will detail the methods used to map micro-kernels selected and developed as part of WP1 onto the macro architecture. The report will define performance metrics for the mapping, report different methods used throughout the project and compare their efficiencies.

First version parallelizing orchestrating compiler targeting CIM micro-instructions

The parallelizing compiler for the CIM architecture will embed skeleton-based and polyhedral compilation techniques into a flexible mapping and code generation framework. The first version of this parallelizing compiler will focus on orchestrating the CIM micro-instructions over the complete architecture, including data layout and the management of data transfer.

First version programming interface at the micro- and macro-levels

Description of micro and macro instruction set.

Initial memristor crossbar based logic/ arithmetic and memory designs and models

The memory compiler models of IMEC will incorporate a few most promising non-volatile memory models, together with behavioural models for sense amplifiers and column/row decoder circuits. These models therefore overcome the limitations of NVSim by generating power/performance/area data which can be applied to a wide range of in-memory computing architecture exploration.

Refined CIM microarchitecture

The technology-aware microarchitecture simulator framework of IMEC will be further extended to incorporate the additional features in the macro-architecture simulator developed of WP 3 and the additional memory compiler models from D4.5 We will also use it for extensive T-A-E design space explorations.

Initial communication protocols and infrastructure

In this report, we will detail the results that will describe the circuits and methods to allow efficient data transfer between tiles and the outside world. The report will detail the challenges, and list the potential solutions that were considered. The circuits methods described in this report will form the basis of the initial system being developed I the project, which will then be refined throughout the project.

First version backend compiler for micro-instructions

First compiler generation of micro instruction for the CIM file.

Final report on new algorithmic solutions

Refine and optimize the new algorithms for the targeted applications while considering the features of the CIM architecture and learning from the results of WP2, WP3 and WP4.

Initial models of memristive device

Based on experimental memristive device characteristics and existing physical device models that are mainly based on continuum models, physical and/or behavioural compact models will be derived for use in circuit simulation. This activity includes model building for both ReRAM devices (RTWH) and PCM devices (IBM), while IMEC will bring in their models as “blackboxes”.

Complete parallelization, orchestration and compilation flow

The deliverable will describe the matured prototypes described in D2.2 and D2.3 and their integration into a unified flow. The flow will be made available to all participants ahead of delivery time and early evaluation will complement the description.

Refined models of memristive device

The initial models will be refined in order to include device “imperfections” as variability, degradation and disturb, as well as statistical property distributions as these will strongly influence the logic performance.

Refined memristor crossbar based logic and memory design and models

The memory compiler models of IMEC will be extended and refined to include more emerging NVM options that are of most promise during this 2nd half of the project.

Report on targeted applications, their specifications, requirements

The report will describe some highly relevant problems arising in the emerging fields of cognitive computing and internet of things (IoT) that could benefit from implementation on non-von Neumann computing architecture based on the computation-in-memory (CIM) dies. The CIM dies could implement digital memristive logic or perform certain arithmetic operations such as vector-matrix multiplication. The report will also describe the application-specific requirements on the CIM dies.

Initial CIM microarchitecture

To enable the technology-aware microarchitecture simulator framework for detailed in-memory computing trade-off exploration, in WP4 a bridge has to be created between the macro-architecture simulator developed as part of WP 3 and the memory compiler models from D4.4.

First report on new algorithmic solutions

Develop new algorithms for the targeted applications while considering the features of the new CIM architecture.

Initial macro CIM architecture and CIM-ISA

Initial ISA description for the whole CIM architecture based on the requirements from D1.1

Websites, patent fillings, videos etc. (2)

Promotional material

Material for publicity and promotion including a project leaflet, a poster, a powerpoint presentation and a short film.

Project website

A project website will be designed, including an external facing website and an internal facing secure cloud storage.

Publicaciones

Peer reviewed articles (16)

In‐Memory Database Query

Autores: Iason Giannopoulos, Abhairaj Singh, Manuel Le Gallo, Vara Prasad Jonnalagadda, Said Hamdioui, Abu Sebastian
Publicado en: Advanced Intelligent Systems, Edición 2/12, 2020, Página(s) 2000141, ISSN 2640-4567
Editor: Wiley-VCH GmbH
DOI: 10.1002/aisy.202000141

Binarization Methods for Motor-Imagery Brain–Computer Interface Classification

Autores: Hersche, Michael; Benini, Luca; Rahimi, Abbas
Publicado en: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 10 (4), Edición 1, 2020, ISSN 2156-3357
Editor: IEEE Circuits and Systems Society
DOI: 10.3929/ethz-b-000457995

Variability-Aware Modeling of Filamentary Oxide based Bipolar Resistive Switching Cells Using SPICE Level Compact Models

Autores: Bengel, Christopher; Siemon, Anne; Cuppers, Felix; Hoffmann-Eifert, Susanne; Hardtdegen, Alexander; Von Witzleben, Moritz; Hellmich, Lena; Waser, Rainer; Menzel, Stephan
Publicado en: IEEE transactions on circuits and systems / 1 67(12), 4618-4630 (2020). doi:10.1109/TCSI.2020.3018502, Edición 17, 2020, Página(s) 4618 - 4630, ISSN 1549-8328
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.18154/rwth-2020-11895

In-memory hyperdimensional computing

Autores: Geethan Karunaratne, Manuel Le Gallo, Giovanni Cherubini, Luca Benini, Abbas Rahimi, Abu Sebastian
Publicado en: Nature Electronics, Edición 3/6, 2020, Página(s) 327-337, ISSN 2520-1131
Editor: Springer Nature
DOI: 10.1038/s41928-020-0410-3

Compressed Sensing With Approximate Message Passing Using In-Memory Computing

Autores: Manuel Le Gallo, Abu Sebastian, Giovanni Cherubini, Heiner Giefers, Evangelos Eleftheriou
Publicado en: IEEE Transactions on Electron Devices, 2018, Página(s) 1-9, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TED.2018.2865352

A phase-change memory model for neuromorphic computing

Autores: S. R. Nandakumar, Manuel Le Gallo, Irem Boybat, Bipin Rajendran, Abu Sebastian, Evangelos Eleftheriou
Publicado en: Journal of Applied Physics, Edición 124/15, 2018, Página(s) 152135, ISSN 0021-8979
Editor: American Institute of Physics
DOI: 10.1063/1.5042408

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing

Autores: Simone Benatti, Fabio Montagna, Victor Kartsch, Abbas Rahimi, Davide Rossi, Luca Benini
Publicado en: IEEE Transactions on Biomedical Circuits and Systems, Edición 13/3, 2019, Página(s) 516-528, ISSN 1932-4545
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbcas.2019.2914476

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Autores: Schmuck, Manuel; Benini, Luca; Rahimi, Abbas
Publicado en: ACM Journal on Emerging Technologies in Computing Systems, Edición 4, 2019, ISSN 1550-4832
Editor: Association for Computing Machinary, Inc.
DOI: 10.3929/ethz-b-000338354

Hyperdimensional Computing with Local Binary Patterns: One-shot Learning for Seizure Onset Detection and Identification of Ictogenic Brain Regions from Short-time iEEG Recordings

Autores: Alessio Burrello, Kaspar Anton Schindler, Luca Benini, Abbas Rahimi
Publicado en: IEEE Transactions on Biomedical Engineering, 2019, Página(s) 1-1, ISSN 0018-9294
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbme.2019.2919137

The Next 700 Accelerated Layers

Autores: Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary Devito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
Publicado en: ACM Transactions on Architecture and Code Optimization, Edición 16/4, 2019, Página(s) 1-26, ISSN 1544-3566
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/3355606

Flextended Tiles

Autores: Jie Zhao, Albert Cohen
Publicado en: ACM Transactions on Architecture and Code Optimization, Edición 16/4, 2019, Página(s) 1-25, ISSN 1544-3566
Editor: Association for Computing Machinary, Inc.
DOI: 10.1145/3369382

Analyses of a 1-layer neuromorphic network using memristive devices with non-continuous resistance levels

Autores: A. Siemon, S. Ferch, A. Heittmann, R. Waser, D. J. Wouters, S. Menzel
Publicado en: APL Materials, Edición 7/9, 2019, Página(s) 091110, ISSN 2166-532X
Editor: AIP Publishing
DOI: 10.1063/1.5108658

Exploiting the switching dynamics of HfO 2 -based ReRAM devices for reliable analog memristive behavior

Autores: F. Cüppers, S. Menzel, C. Bengel, A. Hardtdegen, M. von Witzleben, U. Böttger, R. Waser, S. Hoffmann-Eifert
Publicado en: APL Materials, Edición 7/9, 2019, Página(s) 091105, ISSN 2166-532X
Editor: AIP Publishing
DOI: 10.1063/1.5108654

Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing

Autores: Geethan Karunaratne, Manuel Le Gallo, Michael Hersche, Giovanni Cherubini, Luca Benini, Abu Sebastian, Abbas Rahimi
Publicado en: IEEE Transactions on Circuits and Systems II: Express Briefs, Edición 68/5, 2021, Página(s) 1725-1729, ISSN 1549-7747
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2021.3068126

Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)

Autores: Barak Hoffer, Vikas Rana, Stephan Menzel, Rainer Waser, Shahar Kvatinsky
Publicado en: IEEE Transactions on Electron Devices, Edición 67/8, 2020, Página(s) 3115-3122, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3001247

HRS Instability in Oxide-Based Bipolar Resistive Switching Cells

Autores: Stefan Wiefels, Christopher Bengel, Nils Kopperberg, Kaihua Zhang, Rainer Waser, Stephan Menzel
Publicado en: IEEE Transactions on Electron Devices, Edición 67/10, 2020, Página(s) 4208-4215, ISSN 0018-9383
Editor: Institute of Electrical and Electronics Engineers
DOI: 10.1109/ted.2020.3018096

Conference proceedings (21)

PET-to-MLIR: A polyhedral front-end for MLIR

Autores: Konrad Komisarczyk, Lorenzo Chelini, Kanishkan Vadivel, Roel Jordans, Henk Corporaal
Publicado en: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Página(s) 551-556, ISBN 978-1-7281-9535-3
Editor: IEEE
DOI: 10.1109/dsd51259.2020.00091

Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing: A Low-power Accelerator with Online Capability

Autores: Hersche, Michael; Mello Rella, Edoardo; Di Mauro, Alfio; Benini, Luca; Rahimi, Abbas
Publicado en: ISLPED '20: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Editor: Association for Computing Machinery (ACM)
DOI: 10.3929/ethz-b-000425534

TDO-CIM: Transparent Detection and Offloading for Computation In-memory

Autores: Kanishkan Vadivel, Lorenzo Chelini, Ali BanaGozar, Gagandeep Singh, Stefano Corda, Roel Jordans, Henk Corporaal
Publicado en: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Página(s) 1602-1605, ISBN 978-3-9819263-4-7
Editor: IEEE
DOI: 10.23919/date48585.2020.9116464

Applications of Computation-In-Memory Architectures based on Memristive Devices

Autores: Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando G. Redondo, G. Karunaratne, Abbas Rahimi, Luca Benini
Publicado en: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Página(s) 486-491, ISBN 978-3-9819263-2-3
Editor: IEEE
DOI: 10.23919/DATE.2019.8715020

Time-division Multiplexing Automata Processor

Autores: Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Publicado en: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Página(s) 794-799, ISBN 978-3-9819263-2-3
Editor: IEEE
DOI: 10.23919/date.2019.8715140

Memristive Device Based Circuits for Computation-in-Memory Architectures

Autores: Muath Abu Lebdeh, Uljana Reinsalud, Hoang Anh Du Nguyen, Stephan Wong, Said Hamdioui
Publicado en: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Página(s) 1-5, ISBN 978-1-7281-0397-6
Editor: IEEE
DOI: 10.1109/iscas.2019.8702542

One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing

Autores: Alessio Burrello, Kaspar Schindler, Luca Benini, Abbas Rahimi
Publicado en: 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2018, Página(s) 1-4, ISBN 978-1-5386-3603-9
Editor: IEEE
DOI: 10.1109/BIOCAS.2018.8584751

Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory

Autores: Anne Siemon, Dirk Wouters, Said Hamdioui, Stephan Menzel
Publicado en: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Página(s) 1-5, ISBN 978-1-7281-0397-6
Editor: IEEE
DOI: 10.1109/iscas.2019.8702600

Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms

Autores: Burrello, Alessio; Cavigelli, Lukas; id_orcid0000-0003-1767-7715; Schindler, Kaspar; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Publicado en: Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Edición 4, 2019, ISBN 978-3-9819263-2-3
Editor: IEEE
DOI: 10.3929/ethz-b-000307983

Towards Efficient Code Generation for Exposed Datapath Architectures

Autores: Kanishkan Vadivel, Roel Jordans, Sander Stujik, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala
Publicado en: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Página(s) 86-89, ISBN 9781-450367622
Editor: ACM Press
DOI: 10.1145/3323439.3323990

CIM-SIM - Computation In Memory SIMuIator

Autores: Ali BanaGozar, Kanishkan Vadivel, Sander Stuijk, Henk Corporaal, Stephan Wong, Muath Abu Lebdeh, Jintao Yu, Said Hamdioui
Publicado en: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Página(s) 1-4, ISBN 9781-450367622
Editor: ACM Press
DOI: 10.1145/3323439.3323989

Memristive devices for computation-in-memory

Autores: Jintao Yu, Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui
Publicado en: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Página(s) 1646-1651, ISBN 978-3-9819263-0-9
Editor: IEEE
DOI: 10.23919/date.2018.8342278

A computation-in-memory accelerator based on resistive devices

Autores: Hoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Publicado en: Proceedings of the International Symposium on Memory Systems - MEMSYS '19, 2019, Página(s) 19-32, ISBN 9781-450372060
Editor: ACM Press
DOI: 10.1145/3357526.3357554

Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme

Autores: Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Publicado en: 2019
Editor: IEEE

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics

Autores: Matthew Douthwaite, Fernando Garcia-Redondo, Pantelis Georgiou, Shidhartha Das
Publicado en: 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2019, Página(s) 1-4, ISBN 978-1-5090-0617-5
Editor: IEEE
DOI: 10.1109/BIOCAS.2019.8919190

Evolvable Hyperdimensional Computing: Unsupervised Regeneration of Associative Memory to Recover Faulty Components

Autores: Hersche, Michael; id_orcid0000-0003-3065-7639; Sangalli, Sara; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Publicado en: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Edición 2, 2020
Editor: IEEE
DOI: 10.3929/ethz-b-000387115

Binary Models for Motor-Imagery Brain–Computer Interfaces: Sparse Random Projection and Binarized SVM

Autores: Hersche, Michael; id_orcid0000-0003-3065-7639; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Publicado en: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Edición 1, 2020
Editor: IEEE
DOI: 10.3929/ethz-b-000387116

Compressing Subject-specific Brain–Computer Interface Models into One Model by Superposition in Hyperdimensional Space

Autores: Hersche, Michael; id_orcid0000-0003-3065-7639; Rupp, Philipp; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Publicado en: Design, Automation and Test in Europe (DATE 2020), Edición 1, 2020
Editor: IEEE
DOI: 10.3929/ethz-b-000387117

Training DNN IoT Applications for Deployment On Analog NVM Crossbars

Autores: Fernando Garcia-Redondo, Shidhartha Das, Glen Rosendale
Publicado en: 2020 International Joint Conference on Neural Networks (IJCNN), 2020, Página(s) 1-8, ISBN 978-1-7281-6926-2
Editor: IEEE
DOI: 10.1109/ijcnn48605.2020.9206822

Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM

Autores: Mahdi Zahedi, Mahta Mayahinia, Muath Abu Lebdeh, Stephan Wong, Said Hamdioui
Publicado en: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, Página(s) 216-221, ISBN 978-1-7281-5775-7
Editor: IEEE
DOI: 10.1109/isvlsi49217.2020.00047

TC-CIM: Empowering Tensor Comprehensions for Computing-In-Memory

Autores: A. Drebes, L. Chelini, O. Zinenko, A. Cohen, H. Corporaal, T. Grosser, K. Vadivel, N. Vasilache
Publicado en: Proceedings of 10th International Workshop on Polyhedral Compilation Techniques, 2020
Editor: HiPEAC 2020

Book chapters (1)

System Simulation of Memristor Based Computation in Memory Platforms

Autores: Ali BanaGozar, Kanishkan Vadivel, Joonas Multanen, Pekka Jääskeläinen, Sander Stuijk, Henk Corporaal
Publicado en: Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5–9, 2020, Proceedings, Edición 12471, 2020, Página(s) 152-168, ISBN 978-3-030-60938-2
Editor: Springer International Publishing
DOI: 10.1007/978-3-030-60939-9_11

Other (1)

Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractions

Autores: Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary DeVito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
Publicado en: Computing Research Repository (CoRR), 2018
Editor: Cornell University