From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems | FITOPTIVIS | Project | Results | H2020 | CORDIS

Deliverables

Update of the Dissemination and Communication plan and report

Revised communication and dissemination plan, updating deliverable D8.3. All communication and dissemination activities from M13 to M24 are also reported. Task Involved: ALL

FitOptiVis Gap Analysis

Taking as starting point the test results of the different Use Case demonstrators, this deliverable shall include a gap analysis to identify the missing elements that need to be completed in future stages to develop a full marketable FitOptiVis solution. This deliverable shall also provide general development indications targeted to a transversal FitOptiVis solution as well as domain specific implementation recommendations and recommendations on how to introduce the FitOptiVis developments in the market. Task Involved: 6.3

Preliminary Dissemination and Communication plan and report

Plan for the communication and dissemination activities during and after the project lifetime. The first release will define FitOptiVis preliminary plan (which extends and details what it is already contained in this proposal) and report on activities of WP8 till M12. Task Involved: ALL

Validation and evaluation strategy

In this document a detailed evaluation and validation strategy is recorded. All project objectives and requirements are covered in KPIs and it is determined in which demonstrations they are measured. Task Involved: 1.3

Component models, abstractions, virtualization and methods

This deliverable will report on models, component abstractions, interfaces and virtualization mechanism. The content of this deliverable will provide the key ingredients to achieve MS3. Task Involved: 2.1 and 2.2

Design-time optimization, deployment and programming strategies V1

Report on the activities related to Tasks 3.1-3 regarding i) model-based design and multi-objectves optimization strategies; ii) methods and tools for predicting, simulating and estimating at design-time resource usage; iii) programming and parallelization techniques and iv) coprocessor management. This deliverable contributes to MS3 (M12). Task Involved: All

Final Validation and evaluation report

Update of D1.4 for what regards KPIs report. Task Involved: 1.3

Components Analysis and Specification

This deliverable is meant to report the results of the analysis carried out in T5.1 (see Analysis activity) and T5.3 (see Communication backbone configuration activity) on state of the art and commercial SW and HW components with respect to the use case needs and requirements. Task Involved: 5.1 and 5.3

Final Dissemination and Communication plan and report

Final release of FitOptiVis communication and dissemination plan, updating deliverable D8.5. All communication and dissemination activities from M25 to M36 are also reported. Emphases will be put on the definition of the final plan for the dissemination of foreground. Task Involved: ALL

Design-time optimization, deployment and programming strategies V2

Update of D3.1, Preliminary results will be reported. Open source tools and libraries coming from FitOptiVis studies will be made available with proper user guidelines. This deliverable contributes to MS6 (M24). Task Involved: All

Design-time optimization, deployment and programming strategies V3

Update of D3.2, final assessment of results is reported. Final release of the open source tools and libraries developed within FitOptiVis will be made available with proper user guidelines. This delivearble contributes to MS8 (M34). Task Involved: All

Last project event and End-User Workshop

Final event on FitOptiVis achievements including the final demonstration prototypes presentation.Task Involved: 8.3

First End-User Workshop

Presentation and partial demonstration of FitOptiVis achievements and planned activities to gather useful feedback and guidelines to updated the project directions if necessary. Task Involved: 8.3

Components Release V2

The complete set of innovative processing and communication components developed within the FitOptiVis project are reported and delivered. All the study, development and assessment activities for each of the task are involved. HW and SW physical components implementations, along with their related documentations, are also provided. A subset of the developed IPs (according to the CA and FitOptiVis exploitation plan) will be released open source. Task Involved: All

Second End-User Workshop

Presentation and partial demonstration of FitOptiVis achievements and planned activities to gather useful feedback and guidelines to updated the project directions if necessary. Task Involved: 8.3

FitOptiVis Demonstrators

This deliverable shall include a detailed description on how the common framework is applied for each of the Use Cases and a summary of the obtained results in accordance with the metrics specified in D6.1. These results shall be compared against the requirements prepared in WP1 and the estimations of D6.2, assessing its completeness and relevance. In the same way, the detected limitations of the proposed developments shall be reported. The prototype of each demonstrators will be part of this deliverable. Task Involved: 6.2

Public website and social media channels for the project

Website and social media channels delivery for dissemination, communication and exchange of data outside and inside the consortium. Task Involved: 8.2

Publications

A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources

Author(s): Shayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami, Kees Goossens
Published in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Page(s) 326-329, ISBN 978-3-9819263-4-7
Publisher: IEEE
DOI: 10.23919/date48585.2020.9116514

RF Synchronized Active LED Markers for Reliable Motion Capture

Author(s): R. Čečil, D. Tolar, M. Schlegel
Published in: International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME 2021), 2021
Publisher: IEEE

Reconfigurable Cyber-Physical System for Lifestyle Video-Monitoring via Deep Learning

Author(s): Daniel Deniz, Francisco Barranco, Juan Isern, Eduardo Ros
Published in: 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), 2020, Page(s) 1705-1712, ISBN 978-1-7281-8956-7
Publisher: IEEE
DOI: 10.1109/etfa46521.2020.9211910

Ph.D Forum paper - Design For ReConfigurability: an Electronic System Level Methodology to exploit Reconfigurable Platforms

Author(s): Gabriella D'Andrea, Luigi Pomante
Published in: Virtual Conference FPL2020, 2020
Publisher: IEEE
DOI: 10.1109/fpl50879.2020.00066

Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks

Author(s): Jakub Zadnik, Markku Mäkitalo, Jussi Iho, Pekka Jääskeläinen
Published in: European Workshop on Visual Information Processing 9, 2021
Publisher: N/A

PathTracing: Raising the Level of Understanding of Processing Latency in Heterogeneous MPSoCs

Author(s): Claudion Rubattu, Francesca Palumbo, Shuvra Bhattacharyya, Maxime Pelcat
Published in: Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools Proceedings, 2021, Page(s) 46-50, ISBN 9781450389525
Publisher: ACM
DOI: 10.1145/3444950.3447282

IVIS: Highly customizable framework for visualization and processing of IoT data

Author(s): Lubomir Bulej, Tomas Bures, Petr Hnetynka, Vaclav Camra, Petr Siegl, Michal Topfer
Published in: 2020 46th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 2020, Page(s) 585-588, ISBN 978-1-7281-9532-2
Publisher: IEEE
DOI: 10.1109/seaa51224.2020.00095

A Low Cost and Flexible Power Line Communication Sensory System for Home Automation

Author(s): Mirco Muttillo, Vittoriano Muttillo, Luigi Pomante, Leonardo Pantoli
Published in: 2020 IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2020, Page(s) 191-196, ISBN 978-1-7281-4892-2
Publisher: IEEE
DOI: 10.1109/metroind4.0iot48571.2020.9138191

Runtime reconfigurable system for decommissioned satellite identification and capture

Author(s): R.De Esteban, F. Manteca, M. Martinez and P. Sanchez
Published in: DCIS 2021, 2021
Publisher: IEEE

TTA-SIMD Soft Core Processors

Author(s): Kati Tervo, Samawat Malik, Topi Leppanen, Pekka Jaaskelainen
Published in: 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, Page(s) 79-84, ISBN 978-1-7281-9902-3
Publisher: IEEE
DOI: 10.1109/fpl50879.2020.00023

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI

Author(s): Fanni, Tiziana; Madronal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juarez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi
Published in: FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers, Issue 19, 2019, ISBN 978-3-8007-5045-0
Publisher: VDE VERLAG

Unconstrained License Plate Detection in Hardware

Author(s): Petr Musil, Roman Juránek, Pavel Zemčík
Published in: Proceedings of the 7th International Conference on Vehicle Technology and Intelligent Transport Systems, 2021, Page(s) 13-21, ISBN 978-989-758-513-5
Publisher: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0010174000130021

Adaptive predictive control for pipelined multiprocessor image-based control systems considering workload variations

Author(s): Sajid Mohamed, Nilay Saraf, Daniele Bernardini, Dip Goswami, Twan Basten, Alberto Bemporad
Published in: 2020 59th IEEE Conference on Decision and Control (CDC), 2020, Page(s) 5236-5242, ISBN 978-1-7281-7448-8
Publisher: IEEE
DOI: 10.1109/cdc42340.2020.9303827

Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems

Author(s): Sayandip De, Yingkai Huang, Sajid Mohamed, Dip Goswami, Henk Corporaal
Published in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Page(s) 1751-1756, ISBN 978-3-9819263-5-4
Publisher: IEEE
DOI: 10.23919/date51398.2021.9474216

Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow

Author(s): Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars
Published in: Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings, Issue 11444, 2019, Page(s) 32-47, ISBN 978-3-030-17226-8
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-17227-5_3

Guaranteed latency applications in edge-cloud environment

Author(s): Petr Hnetynka, Petr Kubat, Rima Al-Ali, Ilias Gerostathopoulos, Danylo Khalyeyev
Published in: Proceedings of the 12th European Conference on Software Architecture Companion Proceedings - ECSA '18, 2018, Page(s) 1-4, ISBN 9781-450364836
Publisher: ACM Press
DOI: 10.1145/3241403.3241448

Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable?

Author(s): Gabriella D'Andrea, Tania Di Mascio, Giacomo Valente
Published in: 2019 8th Mediterranean Conference on Embedded Computing (MECO), 2019, Page(s) 1-5, ISBN 978-1-7281-1740-9
Publisher: IEEE
DOI: 10.1109/meco.2019.8760036

Energy-Delay Trade-Offs in Instruction Register File Design

Author(s): Joonas Multanen, Heikki Kultala, Pekka Jaaskelainen
Published in: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, Page(s) 1-7, ISBN 978-1-5386-7656-1
Publisher: IEEE
DOI: 10.1109/norchip.2018.8573504

Reducing Computational Complexity of Real-Time Stereoscopic Ray Tracing with Spatiotemporal Sample Reprojection

Author(s): Markku Mäkitalo, Petrus Kivi, Matias Koskela, Pekka Jääskeläinen
Published in: Proceedings of the 14th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, 2019, Page(s) 367-374, ISBN 978-989-758-354-4
Publisher: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0007692103670374

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory

Author(s): Joonas Multanen, Pekka Jaaskelainen, Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon
Published in: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, Page(s) 1-6, ISBN 978-1-7281-2954-9
Publisher: IEEE
DOI: 10.1109/islped.2019.8824954

Towards Efficient Code Generation for Exposed Datapath Architectures

Author(s): Kanishkan Vadivel, Roel Jordans, Sander Stujik, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala
Published in: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Page(s) 86-89, ISBN 9781-450367622
Publisher: ACM Press
DOI: 10.1145/3323439.3323990

J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW

Author(s): Vittoriano Muttillo
Published in: 2019 8th Mediterranean Conference on Embedded Computing (MECO), 2019, Page(s) 1-5, ISBN 978-1-7281-1740-9
Publisher: IEEE
DOI: 10.1109/meco.2019.8760288

The FitOptiVis ECSEL project - highly efficient distributed embedded image/video processing in cyber-physical systems

Author(s): Zaid Al-Ars, Twan Basten, Ad de Beer, Marc Geilen, Dip Goswami, Pekka Jääskeläinen, Jiří Kadlec, Marcos Martinez de Alejandro, Francesca Palumbo, Geran Peeren, Luigi Pomante, Frank van der Linden, Juka Saarinen, Tero Säntti, Carlo Sau, Maria Katiuscia Zedda
Published in: Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019, Page(s) 333-338, ISBN 9781-450366854
Publisher: ACM
DOI: 10.1145/3310273.3323437

OpenMP Dynamic Device Offloading in Heterogeneous Platforms

Author(s): Ángel Álvarez, Íñigo Ugarte, Víctor Fernández and Pablo Sánchez
Published in: International Workshop on OpenMP (IWOMP), 2019
Publisher: Springer

MECO: an innovative run-time manager to evaluate the Dynamic Partial Reconfiguration profitability

Author(s): Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente
Published in: ACACES 2019 - Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 2019
Publisher: ACACES

Automata Based Test Generation with SpecPro

Author(s): Simone Vuotto, Massimo Narizzano, Luca Pulina, Armando Tacchella
Published in: 2019 IEEE/ACM 6th International Workshop on Requirements Engineering and Testing (RET), 2019, Page(s) 13-16, ISBN 978-1-7281-2274-8
Publisher: IEEE
DOI: 10.1109/ret.2019.00010

Poster: Automatic Consistency Checking of Requirements with ReqV

Author(s): Simone Vuotto, Massimo Narizzano, Luca Pulina, Armando Tacchella
Published in: 2019 12th IEEE Conference on Software Testing, Validation and Verification (ICST), 2019, Page(s) 363-366, ISBN 978-1-7281-1736-2
Publisher: IEEE
DOI: 10.1109/icst.2019.00043

HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions

Author(s): Vittoriano Muttillo, Luigi Pomante, Patricia Balbastre, Jose Simo, Alfons Crespo
Published in: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019, Page(s) 554-561, ISBN 978-1-7281-2862-7
Publisher: IEEE
DOI: 10.1109/dsd.2019.00085

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAP

Author(s): Tiziana Fanni, Daniel Madroñal, Claudio Rubattu, Carlo Sau, Francesca Palumbo, Eduardo Juárez, Maxime Pelcat, César Sanz, Luigi Raffo
Published in: FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers, 2019, ISBN 978-3-8007-5045-0
Publisher: VDE VERLAG

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow

Author(s): Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, Peter Hofstee
Published in: 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, Page(s) 270-277, ISBN 978-1-7281-4884-7
Publisher: IEEE
DOI: 10.1109/fpl.2019.00051

Initial Experiments with Duet Benchmarking: Performance Testing Interference in the Cloud

Author(s): Lubomir Bulej, Vojtech Horky, Petr Tuma
Published in: 2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2019, Page(s) 249-255, ISBN 978-1-7281-4950-9
Publisher: IEEE
DOI: 10.1109/mascots.2019.00035

Duet Benchmarking: Improving Measurement Accuracy in the Cloud

Author(s): Lubomír Bulej, Vojtěch Horký, Petr Tuma, François Farquet, Aleksandar Prokopec
Published in: Proceedings of the ACM/SPEC International Conference on Performance Engineering, 2020, Page(s) 100-107, ISBN 9781-450369916
Publisher: ACM
DOI: 10.1145/3358960.3379132

Foveated Real-Time Path Tracing in Visual-Polar Space

Author(s): Matias Koskela, Atro Lotvonen, Markku Mäkitalo, Petrus Kivi, Pekka Jääskeläinen
Published in: Eurographics Symposium on Rendering 30, 2019
Publisher: Eurographics Symposium on Rendering 30

AEx: Automated Customization of Exposed Datapath Soft-Cores

Author(s): Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen
Published in: Euromicro Conference on Digital System Design 22, 2019
Publisher: Euromicro Conference on Digital System Design 22

Machine Learning is the Solution Also for Foveated Path Tracing Reconstruction

Author(s): Atro Lotvonen, Matias Koskela, Pekka Jääskeläinen
Published in: Proceedings of the 15th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, 2020, Page(s) 361-367, ISBN 978-989-758-402-2
Publisher: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0009156303610367

HIPCL - Tool for Porting CUDA Applications to Advanced OpenCL Platforms Through HIP

Author(s): Michal Babej, Pekka Jääskeläinen
Published in: Proceedings of the International Workshop on OpenCL, 2020, Page(s) 1-3, ISBN 9781-450375313
Publisher: ACM
DOI: 10.1145/3388333.3388641

POCL-R - Distributed OpenCL Runtime for Low Latency Remote Offloading

Author(s): Jan Solanti, Michal Babej, Julius Ikkala, Pekka Jääskeläinen
Published in: Proceedings of the International Workshop on OpenCL, 2020, Page(s) 1-2, ISBN 9781-450375313
Publisher: ACM
DOI: 10.1145/3388333.3388642

Design For ReConfigurability: an Electronic System Level Methodology to exploit Reconfigurable Platforms

Author(s): Gabriella D'Andrea
Published in: 2020
Publisher: Virtual Conference FPL2020

Joint Sparse Recovery of Misaligned Multimodal Images via Adaptive Local and Nonlocal Cross-Modal Regularization

Author(s): Nasser Eslahi, Alessandro Foi
Published in: 2019 IEEE 8th International Workshop on Computational Advances in Multi-Sensor Adaptive Processing (CAMSAP), 2019, Page(s) 111-115, ISBN 978-1-7281-5549-4
Publisher: IEEE
DOI: 10.1109/camsap45676.2019.9022478

Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges

Author(s): Gabriella D'Andrea, Giacomo Valente
Published in: 2020 IEEE Real-Time Systems Symposium (RTSS), 2020, Page(s) 399-402, ISBN 978-1-7281-8324-4
Publisher: IEEE
DOI: 10.1109/rtss49844.2020.00048

QRML: A Component Language and Toolset for Quality and Resource Management

Author(s): Freek van den Berg, Vaclav Camra, Martijn Hendriks, Marc Geilen, Petr Hnetynka, Fernando Manteca, Pablo Sanchez, Tomas Bures, Twan Basten
Published in: 2020 Forum for Specification and Design Languages (FDL), 2020, Page(s) 1-8, ISBN 978-1-7281-8928-4
Publisher: IEEE
DOI: 10.1109/fdl50818.2020.9232936

Layering the monitoring action for improved flexibility and overhead control: work-in-progress

Author(s): Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista
Published in: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2020
Publisher: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
DOI: 10.1109/codesisss51650.2020.9244018

QRD RLS Algorithm for Hand Gesture Recognition Applications

Author(s): Raissa Likhonina
Published in: 2019 International Conference on Systems, Signals and Image Processing (IWSSIP), 2019, Page(s) 195-200, ISBN 978-1-7281-3227-3
Publisher: IEEE
DOI: 10.1109/iwssip.2019.8787283

Design Space Exploration in Heterogeneous Platforms Using OpenMP

Author(s): Angel Alvarez, ́Inigo Ugarte, Victor Fernandez and Pablo Sanchez
Published in: Conference on Design of Circuits and Integrated Systems (DCIS) XXXIV, 2019, ISSN 2640-5563, ISBN 978-1-7281-5459-6
Publisher: IEEE
DOI: 10.1109/dcis201949030.2019.8959934

Automated Requirements-Based Testing of Black-Box Reactive Systems

Author(s): Massimo Narizzano, Luca Pulina, Armando Tacchella, Simone Vuotto
Published in: NASA Formal Methods - 12th International Symposium, NFM 2020, Moffett Field, CA, USA, May 11–15, 2020, Proceedings, Issue 12229, 2020, Page(s) 153-169, ISBN 978-3-030-55753-9
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-55754-6_9

Demo poster paper - JOining flexIble moNitors wiTh hEterogeneous architectuRes

Author(s): G. Valente, T. Fanni, C. Sau, C. Rubattu, F. Palumbo, L. Pomante
Published in: Design, Automation and Test in Europe Conference (DATE), 2020
Publisher: IEEE

A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments

Author(s): Tabatabaei Nikkhah, Shayan; Geilen, Marc; Goswami, Dip; Koedam, Martijn; Nelson, Andrew; Goossens, Kees
Published in: 47nd Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2021), 2021
Publisher: Euromicro Conference on Digital System Design

A Compositional Model for Multi-Rate Max-Plus Linear Systems

Author(s): Hossein Elahi, Marc Geilen, Twan Basten
Published in: IFAC Workshop on Discrete Event Systems (WODES), 2020
Publisher: 15th IFAC Workshop on Discrete Event Systems

FOTV: A Generic Device Offloading Framework for OpenMP

Author(s): Jose Luis Vazquez, Pablo Sanchez
Published in: OpenMP: Enabling Massive Node-Level Parallelism - 17th International Workshop on OpenMP, IWOMP 2021, Bristol, UK, September 14–16, 2021, Proceedings, Issue 12870, 2021, Page(s) 170-182, ISBN 978-3-030-85261-0
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-85262-7_12

Self-adaptive K8S Cloud Controller for Time-sensitive Applications

Author(s): Lubomir Bulej, Tomas Bures, Petr Hnetynka, Danylo Khalyeyev
Published in: 2021 47th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 2021, Page(s) 166-169, ISBN 978-1-6654-2705-0
Publisher: IEEE
DOI: 10.1109/seaa53835.2021.00029

Unified OpenCL Integration Methodology for FPGA Designs

Author(s): Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen
Published in: IEEE Nordic Circuits and Systems Conference, 2021
Publisher: IEEE

Cost-optimized TSN platform for aerospace applications based on RTEMS OS

Author(s): Jorge Sánchez Garrido Luis Medina Valdés Rafael Rodríguez Gómez Javier Díaz
Published in: TSN Applications Conference, 2020
Publisher: WEKA-FACHMEDIEN-EVENTS

Interface Modeling for Quality and Resource Management

Author(s): M. Hendriks, M. Geilen, K. Goossens, R. de Jong, T. Basten
Published in: Logical Methods in Computer Science, LMCS 17(2), Issue Volume 17, Issue 2, 2021, ISSN 1860-5974
Publisher: Technischen Universitat Braunschweig
DOI: 10.23638/lmcs-17(2:19)2021

Reconfigurable cyber-physical system for critical infrastructure protection in smart cities via smart video-surveillance

Author(s): Juan Isern, Francisco Barranco, Daniel Deniz, Juho Lesonen, Jari Hannuksela, Richard R. Carrillo
Published in: Pattern Recognition Letters, Issue 140, 2020, Page(s) 303-309, ISSN 0167-8655
Publisher: Elsevier BV
DOI: 10.1016/j.patrec.2020.11.004

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments

Author(s): Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá-Vayá
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Issue 11733, 2019, Page(s) 3-17, ISSN 1573-7640
Publisher: Springer
DOI: 10.1007/978-3-030-27562-4_1

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Author(s): Francesco Ratto, Tiziana Fanni, Luigi Raffo and Carlo Sau
Published in: Electronics 10 (1), 2021, ISSN 2079-9292
Publisher: MDPI
DOI: 10.3390/electronics10010073

SMT-Based Consistency Checking of Configuration-Based Components Specifications

Author(s): Laura Pandolfo, Luca Pulina, Simone Vuotto
Published in: IEEE Access, Issue 9, 2021, Page(s) 83718-83726, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2021.3085911

Joint direct estimation of 3D geometry and 3D motion using spatio temporal gradients

Author(s): Francisco Barranco, Cornelia Fermüller, Yiannis Aloimonos, Eduardo Ros
Published in: Pattern Recognition, 2020, Page(s) 107759, ISSN 0031-3203
Publisher: Pergamon Press
DOI: 10.1016/j.patcog.2020.107759

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Author(s): Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Published in: Journal of Signal Processing Systems, Issue 93/5, 2021, Page(s) 565-586, ISSN 1939-8018
Publisher: Springer Verlag
DOI: 10.1007/s11265-021-01650-6

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Author(s): Carlo Sau, Tiziana Fanni, Claudio Rubattu, Luigi Raffo, Francesca Palumbo
Published in: Microprocessors and Microsystems, Issue 80, 2021, Page(s) 103326, ISSN 0141-9331
Publisher: Elsevier BV
DOI: 10.1016/j.micpro.2020.103326

Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory

Author(s): Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jaaskelainen
Published in: IEEE Transactions on Computers, 2021, Page(s) 1-1, ISSN 0018-9340
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2021.3117439

EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation

Author(s): Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Santti, Lauri Koskinen
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Issue 29/6, 2021, Page(s) 1061-1072, ISSN 1063-8210
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2021.3070687

An early-stage statement-level metric for energy characterization of embedded processors

Author(s): Vittoriano Muttillo, Paolo Giammatteo, Vincenzo Stoico, Luigi Pomante
Published in: Microprocessors and Microsystems, Issue 77, 2020, Page(s) 103200, ISSN 0141-9331
Publisher: Elsevier BV
DOI: 10.1016/j.micpro.2020.103200

An integrated hardware/software design methodology for signal processing systems

Author(s): Lin Li, Carlo Sau, Tiziana Fanni, Jingui Li, Timo Viitanen, François Christophe, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala, Shuvra S. Bhattacharyya
Published in: Journal of Systems Architecture, Issue 93, 2019, Page(s) 1-19, ISSN 1383-7621
Publisher: Elsevier BV
DOI: 10.1016/j.sysarc.2018.12.010

Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction

Author(s): Matias Koskela, Kalle Immonen, Markku Mäkitalo, Alessandro Foi, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala
Published in: ACM Transactions on Graphics, Issue 38/5, 2019, Page(s) 1-14, ISSN 0730-0301
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3269978

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding

Author(s): Carlo Sau, Dario Ligas, Tiziana Fanni, Luigi Raffo, Francesca Palumbo
Published in: IEEE Access, Issue 7, 2019, Page(s) 153258-153268, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2019.2946054

A scenario- and platform-aware design flow for image-based control systems

Author(s): Sajid Mohamed, Dip Goswami, Vishak Nathan, Raghu Rajappa, Twan Basten
Published in: Microprocessors and Microsystems, Issue 75, 2020, Page(s) 103037, ISSN 0141-9331
Publisher: Elsevier BV
DOI: 10.1016/j.micpro.2020.103037

Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Author(s): Giacomo Valente, Tania Di Mascio, Gabriella DrAndrea, Luigi Pomante
Published in: IEEE Embedded Systems Letters, 2020, Page(s) 1-1, ISSN 1943-0663
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/les.2020.3004302

Approximation-Aware Design of an Image-Based Control System

Author(s): Sayandip De, Sajid Mohamed, Dip Goswami, Henk Corporaal
Published in: IEEE Access, Issue 8, 2020, Page(s) 174568-174586, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3023047

Tydi: An Open Specification for Complex Data Structures Over Hardware Streams

Author(s): Johan Peltenburg, Jeroen Van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Published in: IEEE Micro, Issue 40/4, 2020, Page(s) 120-130, ISSN 0272-1732
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2020.2996373

Managing latency in edge–cloud environment

Author(s): Lubomír Bulej, Tomáš Bureš, Adam Filandr, Petr Hnětynka, Iveta Hnětynková, Jan Pacovský, Gabor Sandor, Ilias Gerostathopoulos
Published in: Journal of Systems and Software, Issue 172, 2021, Page(s) 110872, ISSN 0164-1212
Publisher: Elsevier BV
DOI: 10.1016/j.jss.2020.110872

Optimising Multiprocessor Image-Based Control Through Pipelining and Parallelism

Author(s): Sajid Mohamed, Dip Goswami, Sayandip De, Twan Basten
Published in: IEEE Access, Issue 9, 2021, Page(s) 112332-112358, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2021.3103051

DTRiMC tool for TE0726-03M board

Author(s): Kadlec Jiri, Likhonina Raissa
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

Full HD 60 FPS License plate detector for Zynq platform

Author(s): Musil Petr, Juránek Roman, Zemčík Pavel
Published in: Brno University of Technology, 2019
Publisher: Brno University of Technology

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project

Author(s): Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jiri Kadlec, Pekka Jaaskelainen, Marcos Martinez, Jukka Saarinen, Tero Santti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer
Published in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Page(s) 378-385, ISBN 978-1-7281-9535-3
Publisher: IEEE
DOI: 10.1109/dsd51259.2020.00067

DDISH-GI: Dynamic Distributed Spherical Harmonics Global Illumination

Author(s): Julius Ikkala, Petrus Kivi, Joel Alanko, Markku Mäkitalo and Pekka Jääskeläinen
Published in: Computer Graphics International, 2021
Publisher: Computer Graphics International

FP01x8 Accelerator on TE0726-03M

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Published in: 2019
Publisher: UTIA AV CR, v.v.i.

Lightweight profiler for embedded systems

Author(s): Musil Petr, Juránek Roman, Zemčík Pavel
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

Waldboost package for Python

Author(s): Roman Juranek
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency

Author(s): Joonas Multanen, Kari Hepola, Pekka Jaaskelainen
Published in: 2020 IEEE 38th International Conference on Computer Design (ICCD), 2020, Page(s) 356-363, ISBN 978-1-7281-9710-4
Publisher: IEEE
DOI: 10.1109/iccd50377.2020.00066

Performing Electromagnetic Side-channel Attack On A Commercial AES-256 Device

Author(s): Mika Kaustinen, Ohto Myllynen, Tero Jokela, Lauri Koskinen, Olli Heimo and Tero Säntti
Published in: Technical Report, 2021, ISBN 978-951-29-8653-8
Publisher: University of Turku

DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board

Author(s): Kadlec Jiri, Likhonina Raissa
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

Probabilistic Pose Estimation from Multiple Hypotheses

Author(s): Escrivá, David & Perez-Jimenez, Alberto & Pérez Soler, Javier & Del Tejo Catalá, Omar & Perez-Cortes, Juan-Carlos & Guardiola, Jose-Luis.
Published in: 2021
Publisher: N/A
DOI: 10.13140/rg.2.2.21609.21609

HDR merging and deghosting firmware

Author(s): Musil Martin, Nosko Svetozár
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

Design Time and Run Time Resources for the ZynqBerry Board TE0726-03M with SDSoC 2018.2 Support

Author(s): Kadlec, Jiri; Pohl, Zdenek; Kohout, Lukas
Published in: UTIA in FitOptiVis, 2019
Publisher: UTIA AV CR, v.v.i.

Live Canny Edge Detection Demo for TE0808+TEBF0808 Trenz Board

Author(s): Pohl, Zdenek; Kohout, Lukas; Kadlec, Jiri
Published in: UTIA in FitOptiVis, 2018
Publisher: UTIA AV CR, v.v.i.

Design Time and Run Time Resources for Zynq Ultrascale+ TE0820-03-4EV-1E with SDSoC 2018.2 Support

Author(s): Kadlec, Jiri; Pohl, Zdenek; Kohout, Lukas
Published in: UTIA in FitOptiVis, 2019
Publisher: UTIA AV CR, v.v.i.

Stereo Demo

Author(s): Pohl, Zdenek; Kohout, Lukas; Kadlec, Jiri
Published in: UTIA in FitOptiVis, 2018
Publisher: UTIA AV CR, v.v.i.

Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module

Author(s): Kohout, Lukas; Kadlec, Jiri; Pohl, Zdenek
Published in: UTIA in FitOptiVis, 2019
Publisher: UTIA AV CR, v.v.i.

Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module

Author(s): Kohout, Lukas; Kadlec, Jiri; Pohl, Zdenek
Published in: UTIA in FitOptiVis, 2019
Publisher: UTIA AV CR, v.v.i.

Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support

Author(s): Kadlec, Jiri;, Pohl, Zdenek; Kohout, Lukas
Published in: UTIA in FitOptiVis, 2019
Publisher: UTIA AV CR, v.v.i.

AN AUTONOMIC MANAGER FOR EDGE-COMPUTING PLATFORMS

Author(s): Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente
Published in: 2019
Publisher: DATE

HDR Tonemapping demo

Author(s): Martin Musil, Svetozar Nosko
Published in: 2019
Publisher: BUT

HDR deghosting demo

Author(s): Martin Musil, Petr Musil
Published in: 2019
Publisher: BUT

FPGA object detection demo

Author(s): Petr Musil, Roman Juranek
Published in: 2019
Publisher: BUT

HEPSYCODE-MC: ELECTRONIC SYSTEM-LEVEL METHODOLOGY FOR HW/SW CO-DESIGN OF MIXED-CRITICALITY EMBEDDED SYSTEMS

Author(s): Luigi Pomante, Vittoriano Muttillo, Marco Santic and Emilio Incerto
Published in: Conference on Design and Test Automation in Europe (DATE), 2019
Publisher: DATE

ESL HW/SW Co-Design Methodology for Mixed-Criticality and Real-Time Embedded Systems

Author(s): Vittoriano Muttillo
Published in: Conference on Design and Test Automation in Europe (DATE), 2019
Publisher: DATE

Tutorial HEPSYCODE PhD Course

Author(s): Vittoriano Muttillo, Luigi Pomante
Published in: Seminar at Università degli Studi dell'Aquila, 2019
Publisher: Università degli Studi dell'Aquila

MECO AN INNOVATIVE RUN-TIME MANAGER TO EVALUATE THE DYNAMIC PARTIAL RECONFIGURATION PROFITABILITY

Author(s): Gabriella D'Andrea
Published in: CWWMCA19 - Career Workshop for Women & Minorities in Computer Architecture, 2019
Publisher: CWWMCA19

Design space exploration for hypervisor-based mixed-criticality systems

Author(s): V. Muttillo, L. Pomante
Published in: CPS&IoT’2019 Summer School on Cyber-Physical Systems and Internet-of-Things, 2019
Publisher: CPS&IoT’2019

JOINTER JOining flexIble moNitors wiTh hEterogeneous architectuRes

Author(s): G. Valente, T. Fanni, C. Sau, C. Rubattu, F. Palumbo, L. Pomante
Published in: DATE2020 Design, Automation and Test in Europe Conference, 2020
Publisher: DATE

Data Movers in DTRiMC tool for TE0726 03M 07S board

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas, Likhonina Raissa
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime

Author(s): Jan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen
Published in: Embedded Computer Systems: Architectures, MOdeling, and Simulation 21, 2021
Publisher: OPENAIRE
DOI: 10.5281/zenodo.5091763

ACF object detector for FPGA

Author(s): Musil Petr, Juránek Roman, Zemčík Pavel
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

Computer Vision on the edge to reduce network bandwidth and computing resources in multi-view 3D industrial inspection without hidden surfaces. (in review)

Author(s): David Millán Escrivá, Javier Perez Soler, Jose Luis Guardiola, Juan Carlos Pérez Cortés.
Published in: Microprocessors and Microsystems, 2022, ISSN 0141-9331
Publisher: Elsevier BV

A Composable Monitoring System for Heterogeneous Embedded Platforms

Author(s): Giacomo Valente, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, Francesca Palumbo
Published in: ACM Transactions on Embedded Computing Systems, Issue 20/5, 2021, Page(s) 1-34, ISSN 1539-9087
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3461647

Radar Signal Processing and Fusion of Information

Author(s): Reich Bořek
Published in: Brno University of Technology, 2020
Publisher: Brno University of Technology

Two serial connected evaluation versions of FP03x8 accelerators for TE0820-03-4EV-1E module on TE0701-06 carrier board

Author(s): Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Published in: 2019
Publisher: UTIA AV CR, v.v.i.

Hardware acceleration of object detection in images

Author(s): Petr Musil
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

Diseño de un sistema de reconocimiento automático de comportamientos humanos basado en vídeo mediante redes neuronales recurrentes / Design of human activity recognition engine based on video analisis with Recurrent Neural Networks

Author(s): Javier W. Ortiz Canepa
Published in: 2021, Page(s) 0-71
Publisher: Universidad Politécnica de Madrid

Ensuring Precision of Stereo Image Processing

Author(s): Kuník Oliver
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

Ghost-free HDR video using FPGA

Author(s): Martin Musil
Published in: Brno University of Technology, 2021
Publisher: Brno University of Technology

Eight FP03x8 accelerators for TE0808-09-EG-ES1 module on TEBF0808 carrier board

Author(s): Kadlec Jiri
Published in: 2021
Publisher: UTIA AV CR, v.v.i.

Classification of Varying-Size Plankton Images with Convolutional Neural Network

Author(s): Bureš Jaroslav
Published in: Brno University of Technology, 2020
Publisher: Brno University of Technology

Methods for Efficient Integration of FPGA Accelerators with Big Data Systems

Author(s): J.W. Peltenburg
Published in: 2020, ISBN 978-94-6366-333-5
Publisher: Delft University of Technology
DOI: 10.4233/uuid:51989f8f-f672-4f4b-a059-86233869ff47

Reconfigurable and approximate computing for video coding

Author(s): Francesca Palumbo, Carlo Sau
Published in: VLSI Architectures for Future Video Coding, 2019
Publisher: Institution of Engineering and Technology

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