From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems | FITOPTIVIS | Project | Results | H2020 | CORDIS

Risultati finali

Update of the Dissemination and Communication plan and report

Revised communication and dissemination plan, updating deliverable D8.3. All communication and dissemination activities from M13 to M24 are also reported. Task Involved: ALL

FitOptiVis Gap Analysis

Taking as starting point the test results of the different Use Case demonstrators, this deliverable shall include a gap analysis to identify the missing elements that need to be completed in future stages to develop a full marketable FitOptiVis solution. This deliverable shall also provide general development indications targeted to a transversal FitOptiVis solution as well as domain specific implementation recommendations and recommendations on how to introduce the FitOptiVis developments in the market. Task Involved: 6.3

Preliminary Dissemination and Communication plan and report

Plan for the communication and dissemination activities during and after the project lifetime. The first release will define FitOptiVis preliminary plan (which extends and details what it is already contained in this proposal) and report on activities of WP8 till M12. Task Involved: ALL

Validation and evaluation strategy

In this document a detailed evaluation and validation strategy is recorded. All project objectives and requirements are covered in KPIs and it is determined in which demonstrations they are measured. Task Involved: 1.3

Component models, abstractions, virtualization and methods

This deliverable will report on models, component abstractions, interfaces and virtualization mechanism. The content of this deliverable will provide the key ingredients to achieve MS3. Task Involved: 2.1 and 2.2

Design-time optimization, deployment and programming strategies V1

Report on the activities related to Tasks 3.1-3 regarding i) model-based design and multi-objectves optimization strategies; ii) methods and tools for predicting, simulating and estimating at design-time resource usage; iii) programming and parallelization techniques and iv) coprocessor management. This deliverable contributes to MS3 (M12). Task Involved: All

Final Validation and evaluation report

Update of D1.4 for what regards KPIs report. Task Involved: 1.3

Components Analysis and Specification

This deliverable is meant to report the results of the analysis carried out in T5.1 (see Analysis activity) and T5.3 (see Communication backbone configuration activity) on state of the art and commercial SW and HW components with respect to the use case needs and requirements. Task Involved: 5.1 and 5.3

Final Dissemination and Communication plan and report

Final release of FitOptiVis communication and dissemination plan, updating deliverable D8.5. All communication and dissemination activities from M25 to M36 are also reported. Emphases will be put on the definition of the final plan for the dissemination of foreground. Task Involved: ALL

Design-time optimization, deployment and programming strategies V2

Update of D3.1, Preliminary results will be reported. Open source tools and libraries coming from FitOptiVis studies will be made available with proper user guidelines. This deliverable contributes to MS6 (M24). Task Involved: All

Design-time optimization, deployment and programming strategies V3

Update of D3.2, final assessment of results is reported. Final release of the open source tools and libraries developed within FitOptiVis will be made available with proper user guidelines. This delivearble contributes to MS8 (M34). Task Involved: All

Last project event and End-User Workshop

Final event on FitOptiVis achievements including the final demonstration prototypes presentation.Task Involved: 8.3

First End-User Workshop

Presentation and partial demonstration of FitOptiVis achievements and planned activities to gather useful feedback and guidelines to updated the project directions if necessary. Task Involved: 8.3

Components Release V2

The complete set of innovative processing and communication components developed within the FitOptiVis project are reported and delivered. All the study, development and assessment activities for each of the task are involved. HW and SW physical components implementations, along with their related documentations, are also provided. A subset of the developed IPs (according to the CA and FitOptiVis exploitation plan) will be released open source. Task Involved: All

Second End-User Workshop

Presentation and partial demonstration of FitOptiVis achievements and planned activities to gather useful feedback and guidelines to updated the project directions if necessary. Task Involved: 8.3

FitOptiVis Demonstrators

This deliverable shall include a detailed description on how the common framework is applied for each of the Use Cases and a summary of the obtained results in accordance with the metrics specified in D6.1. These results shall be compared against the requirements prepared in WP1 and the estimations of D6.2, assessing its completeness and relevance. In the same way, the detected limitations of the proposed developments shall be reported. The prototype of each demonstrators will be part of this deliverable. Task Involved: 6.2

Public website and social media channels for the project

Website and social media channels delivery for dissemination, communication and exchange of data outside and inside the consortium. Task Involved: 8.2

Pubblicazioni

A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources

Autori: Shayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami, Kees Goossens
Pubblicato in: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, Pagina/e 326-329, ISBN 978-3-9819263-4-7
Editore: IEEE
DOI: 10.23919/date48585.2020.9116514

RF Synchronized Active LED Markers for Reliable Motion Capture

Autori: R. Čečil, D. Tolar, M. Schlegel
Pubblicato in: International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME 2021), 2021
Editore: IEEE

Reconfigurable Cyber-Physical System for Lifestyle Video-Monitoring via Deep Learning

Autori: Daniel Deniz, Francisco Barranco, Juan Isern, Eduardo Ros
Pubblicato in: 2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), 2020, Pagina/e 1705-1712, ISBN 978-1-7281-8956-7
Editore: IEEE
DOI: 10.1109/etfa46521.2020.9211910

Ph.D Forum paper - Design For ReConfigurability: an Electronic System Level Methodology to exploit Reconfigurable Platforms

Autori: Gabriella D'Andrea, Luigi Pomante
Pubblicato in: Virtual Conference FPL2020, 2020
Editore: IEEE
DOI: 10.1109/fpl50879.2020.00066

Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks

Autori: Jakub Zadnik, Markku Mäkitalo, Jussi Iho, Pekka Jääskeläinen
Pubblicato in: European Workshop on Visual Information Processing 9, 2021
Editore: N/A

PathTracing: Raising the Level of Understanding of Processing Latency in Heterogeneous MPSoCs

Autori: Claudion Rubattu, Francesca Palumbo, Shuvra Bhattacharyya, Maxime Pelcat
Pubblicato in: Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools Proceedings, 2021, Pagina/e 46-50, ISBN 9781450389525
Editore: ACM
DOI: 10.1145/3444950.3447282

IVIS: Highly customizable framework for visualization and processing of IoT data

Autori: Lubomir Bulej, Tomas Bures, Petr Hnetynka, Vaclav Camra, Petr Siegl, Michal Topfer
Pubblicato in: 2020 46th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 2020, Pagina/e 585-588, ISBN 978-1-7281-9532-2
Editore: IEEE
DOI: 10.1109/seaa51224.2020.00095

A Low Cost and Flexible Power Line Communication Sensory System for Home Automation

Autori: Mirco Muttillo, Vittoriano Muttillo, Luigi Pomante, Leonardo Pantoli
Pubblicato in: 2020 IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2020, Pagina/e 191-196, ISBN 978-1-7281-4892-2
Editore: IEEE
DOI: 10.1109/metroind4.0iot48571.2020.9138191

Runtime reconfigurable system for decommissioned satellite identification and capture

Autori: R.De Esteban, F. Manteca, M. Martinez and P. Sanchez
Pubblicato in: DCIS 2021, 2021
Editore: IEEE

TTA-SIMD Soft Core Processors

Autori: Kati Tervo, Samawat Malik, Topi Leppanen, Pekka Jaaskelainen
Pubblicato in: 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, Pagina/e 79-84, ISBN 978-1-7281-9902-3
Editore: IEEE
DOI: 10.1109/fpl50879.2020.00023

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI

Autori: Fanni, Tiziana; Madronal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juarez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi
Pubblicato in: FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers, Numero 19, 2019, ISBN 978-3-8007-5045-0
Editore: VDE VERLAG

Unconstrained License Plate Detection in Hardware

Autori: Petr Musil, Roman Juránek, Pavel Zemčík
Pubblicato in: Proceedings of the 7th International Conference on Vehicle Technology and Intelligent Transport Systems, 2021, Pagina/e 13-21, ISBN 978-989-758-513-5
Editore: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0010174000130021

Adaptive predictive control for pipelined multiprocessor image-based control systems considering workload variations

Autori: Sajid Mohamed, Nilay Saraf, Daniele Bernardini, Dip Goswami, Twan Basten, Alberto Bemporad
Pubblicato in: 2020 59th IEEE Conference on Decision and Control (CDC), 2020, Pagina/e 5236-5242, ISBN 978-1-7281-7448-8
Editore: IEEE
DOI: 10.1109/cdc42340.2020.9303827

Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems

Autori: Sayandip De, Yingkai Huang, Sajid Mohamed, Dip Goswami, Henk Corporaal
Pubblicato in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, Pagina/e 1751-1756, ISBN 978-3-9819263-5-4
Editore: IEEE
DOI: 10.23919/date51398.2021.9474216

Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow

Autori: Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars
Pubblicato in: Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings, Numero 11444, 2019, Pagina/e 32-47, ISBN 978-3-030-17226-8
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-17227-5_3

Guaranteed latency applications in edge-cloud environment

Autori: Petr Hnetynka, Petr Kubat, Rima Al-Ali, Ilias Gerostathopoulos, Danylo Khalyeyev
Pubblicato in: Proceedings of the 12th European Conference on Software Architecture Companion Proceedings - ECSA '18, 2018, Pagina/e 1-4, ISBN 9781-450364836
Editore: ACM Press
DOI: 10.1145/3241403.3241448

Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable?

Autori: Gabriella D'Andrea, Tania Di Mascio, Giacomo Valente
Pubblicato in: 2019 8th Mediterranean Conference on Embedded Computing (MECO), 2019, Pagina/e 1-5, ISBN 978-1-7281-1740-9
Editore: IEEE
DOI: 10.1109/meco.2019.8760036

Energy-Delay Trade-Offs in Instruction Register File Design

Autori: Joonas Multanen, Heikki Kultala, Pekka Jaaskelainen
Pubblicato in: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, Pagina/e 1-7, ISBN 978-1-5386-7656-1
Editore: IEEE
DOI: 10.1109/norchip.2018.8573504

Reducing Computational Complexity of Real-Time Stereoscopic Ray Tracing with Spatiotemporal Sample Reprojection

Autori: Markku Mäkitalo, Petrus Kivi, Matias Koskela, Pekka Jääskeläinen
Pubblicato in: Proceedings of the 14th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, 2019, Pagina/e 367-374, ISBN 978-989-758-354-4
Editore: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0007692103670374

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory

Autori: Joonas Multanen, Pekka Jaaskelainen, Asif Ali Khan, Fazal Hameed, Jeronimo Castrillon
Pubblicato in: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, Pagina/e 1-6, ISBN 978-1-7281-2954-9
Editore: IEEE
DOI: 10.1109/islped.2019.8824954

Towards Efficient Code Generation for Exposed Datapath Architectures

Autori: Kanishkan Vadivel, Roel Jordans, Sander Stujik, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala
Pubblicato in: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Pagina/e 86-89, ISBN 9781-450367622
Editore: ACM Press
DOI: 10.1145/3323439.3323990

J4CS: An Early-Stage Statement-Level Metric for Energy Consumption of Embedded SW

Autori: Vittoriano Muttillo
Pubblicato in: 2019 8th Mediterranean Conference on Embedded Computing (MECO), 2019, Pagina/e 1-5, ISBN 978-1-7281-1740-9
Editore: IEEE
DOI: 10.1109/meco.2019.8760288

The FitOptiVis ECSEL project - highly efficient distributed embedded image/video processing in cyber-physical systems

Autori: Zaid Al-Ars, Twan Basten, Ad de Beer, Marc Geilen, Dip Goswami, Pekka Jääskeläinen, Jiří Kadlec, Marcos Martinez de Alejandro, Francesca Palumbo, Geran Peeren, Luigi Pomante, Frank van der Linden, Juka Saarinen, Tero Säntti, Carlo Sau, Maria Katiuscia Zedda
Pubblicato in: Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019, Pagina/e 333-338, ISBN 9781-450366854
Editore: ACM
DOI: 10.1145/3310273.3323437

OpenMP Dynamic Device Offloading in Heterogeneous Platforms

Autori: Ángel Álvarez, Íñigo Ugarte, Víctor Fernández and Pablo Sánchez
Pubblicato in: International Workshop on OpenMP (IWOMP), 2019
Editore: Springer

MECO: an innovative run-time manager to evaluate the Dynamic Partial Reconfiguration profitability

Autori: Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente
Pubblicato in: ACACES 2019 - Fifteenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 2019
Editore: ACACES

Automata Based Test Generation with SpecPro

Autori: Simone Vuotto, Massimo Narizzano, Luca Pulina, Armando Tacchella
Pubblicato in: 2019 IEEE/ACM 6th International Workshop on Requirements Engineering and Testing (RET), 2019, Pagina/e 13-16, ISBN 978-1-7281-2274-8
Editore: IEEE
DOI: 10.1109/ret.2019.00010

Poster: Automatic Consistency Checking of Requirements with ReqV

Autori: Simone Vuotto, Massimo Narizzano, Luca Pulina, Armando Tacchella
Pubblicato in: 2019 12th IEEE Conference on Software Testing, Validation and Verification (ICST), 2019, Pagina/e 363-366, ISBN 978-1-7281-1736-2
Editore: IEEE
DOI: 10.1109/icst.2019.00043

HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions

Autori: Vittoriano Muttillo, Luigi Pomante, Patricia Balbastre, Jose Simo, Alfons Crespo
Pubblicato in: 2019 22nd Euromicro Conference on Digital System Design (DSD), 2019, Pagina/e 554-561, ISBN 978-1-7281-2862-7
Editore: IEEE
DOI: 10.1109/dsd.2019.00085

Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAP

Autori: Tiziana Fanni, Daniel Madroñal, Claudio Rubattu, Carlo Sau, Francesca Palumbo, Eduardo Juárez, Maxime Pelcat, César Sanz, Luigi Raffo
Pubblicato in: FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers, 2019, ISBN 978-3-8007-5045-0
Editore: VDE VERLAG

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow

Autori: Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, Peter Hofstee
Pubblicato in: 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, Pagina/e 270-277, ISBN 978-1-7281-4884-7
Editore: IEEE
DOI: 10.1109/fpl.2019.00051

Initial Experiments with Duet Benchmarking: Performance Testing Interference in the Cloud

Autori: Lubomir Bulej, Vojtech Horky, Petr Tuma
Pubblicato in: 2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2019, Pagina/e 249-255, ISBN 978-1-7281-4950-9
Editore: IEEE
DOI: 10.1109/mascots.2019.00035

Duet Benchmarking: Improving Measurement Accuracy in the Cloud

Autori: Lubomír Bulej, Vojtěch Horký, Petr Tuma, François Farquet, Aleksandar Prokopec
Pubblicato in: Proceedings of the ACM/SPEC International Conference on Performance Engineering, 2020, Pagina/e 100-107, ISBN 9781-450369916
Editore: ACM
DOI: 10.1145/3358960.3379132

Foveated Real-Time Path Tracing in Visual-Polar Space

Autori: Matias Koskela, Atro Lotvonen, Markku Mäkitalo, Petrus Kivi, Pekka Jääskeläinen
Pubblicato in: Eurographics Symposium on Rendering 30, 2019
Editore: Eurographics Symposium on Rendering 30

AEx: Automated Customization of Exposed Datapath Soft-Cores

Autori: Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen
Pubblicato in: Euromicro Conference on Digital System Design 22, 2019
Editore: Euromicro Conference on Digital System Design 22

Machine Learning is the Solution Also for Foveated Path Tracing Reconstruction

Autori: Atro Lotvonen, Matias Koskela, Pekka Jääskeläinen
Pubblicato in: Proceedings of the 15th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, 2020, Pagina/e 361-367, ISBN 978-989-758-402-2
Editore: SCITEPRESS - Science and Technology Publications
DOI: 10.5220/0009156303610367

HIPCL - Tool for Porting CUDA Applications to Advanced OpenCL Platforms Through HIP

Autori: Michal Babej, Pekka Jääskeläinen
Pubblicato in: Proceedings of the International Workshop on OpenCL, 2020, Pagina/e 1-3, ISBN 9781-450375313
Editore: ACM
DOI: 10.1145/3388333.3388641

POCL-R - Distributed OpenCL Runtime for Low Latency Remote Offloading

Autori: Jan Solanti, Michal Babej, Julius Ikkala, Pekka Jääskeläinen
Pubblicato in: Proceedings of the International Workshop on OpenCL, 2020, Pagina/e 1-2, ISBN 9781-450375313
Editore: ACM
DOI: 10.1145/3388333.3388642

Design For ReConfigurability: an Electronic System Level Methodology to exploit Reconfigurable Platforms

Autori: Gabriella D'Andrea
Pubblicato in: 2020
Editore: Virtual Conference FPL2020

Joint Sparse Recovery of Misaligned Multimodal Images via Adaptive Local and Nonlocal Cross-Modal Regularization

Autori: Nasser Eslahi, Alessandro Foi
Pubblicato in: 2019 IEEE 8th International Workshop on Computational Advances in Multi-Sensor Adaptive Processing (CAMSAP), 2019, Pagina/e 111-115, ISBN 978-1-7281-5549-4
Editore: IEEE
DOI: 10.1109/camsap45676.2019.9022478

Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges

Autori: Gabriella D'Andrea, Giacomo Valente
Pubblicato in: 2020 IEEE Real-Time Systems Symposium (RTSS), 2020, Pagina/e 399-402, ISBN 978-1-7281-8324-4
Editore: IEEE
DOI: 10.1109/rtss49844.2020.00048

QRML: A Component Language and Toolset for Quality and Resource Management

Autori: Freek van den Berg, Vaclav Camra, Martijn Hendriks, Marc Geilen, Petr Hnetynka, Fernando Manteca, Pablo Sanchez, Tomas Bures, Twan Basten
Pubblicato in: 2020 Forum for Specification and Design Languages (FDL), 2020, Pagina/e 1-8, ISBN 978-1-7281-8928-4
Editore: IEEE
DOI: 10.1109/fdl50818.2020.9232936

Layering the monitoring action for improved flexibility and overhead control: work-in-progress

Autori: Giacomo Valente, Tiziana Fanni, Carlo Sau, Francesco Di Battista
Pubblicato in: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2020
Editore: 2020 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
DOI: 10.1109/codesisss51650.2020.9244018

QRD RLS Algorithm for Hand Gesture Recognition Applications

Autori: Raissa Likhonina
Pubblicato in: 2019 International Conference on Systems, Signals and Image Processing (IWSSIP), 2019, Pagina/e 195-200, ISBN 978-1-7281-3227-3
Editore: IEEE
DOI: 10.1109/iwssip.2019.8787283

Design Space Exploration in Heterogeneous Platforms Using OpenMP

Autori: Angel Alvarez, ́Inigo Ugarte, Victor Fernandez and Pablo Sanchez
Pubblicato in: Conference on Design of Circuits and Integrated Systems (DCIS) XXXIV, 2019, ISSN 2640-5563, ISBN 978-1-7281-5459-6
Editore: IEEE
DOI: 10.1109/dcis201949030.2019.8959934

Automated Requirements-Based Testing of Black-Box Reactive Systems

Autori: Massimo Narizzano, Luca Pulina, Armando Tacchella, Simone Vuotto
Pubblicato in: NASA Formal Methods - 12th International Symposium, NFM 2020, Moffett Field, CA, USA, May 11–15, 2020, Proceedings, Numero 12229, 2020, Pagina/e 153-169, ISBN 978-3-030-55753-9
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-55754-6_9

Demo poster paper - JOining flexIble moNitors wiTh hEterogeneous architectuRes

Autori: G. Valente, T. Fanni, C. Sau, C. Rubattu, F. Palumbo, L. Pomante
Pubblicato in: Design, Automation and Test in Europe Conference (DATE), 2020
Editore: IEEE

A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments

Autori: Tabatabaei Nikkhah, Shayan; Geilen, Marc; Goswami, Dip; Koedam, Martijn; Nelson, Andrew; Goossens, Kees
Pubblicato in: 47nd Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2021), 2021
Editore: Euromicro Conference on Digital System Design

A Compositional Model for Multi-Rate Max-Plus Linear Systems

Autori: Hossein Elahi, Marc Geilen, Twan Basten
Pubblicato in: IFAC Workshop on Discrete Event Systems (WODES), 2020
Editore: 15th IFAC Workshop on Discrete Event Systems

FOTV: A Generic Device Offloading Framework for OpenMP

Autori: Jose Luis Vazquez, Pablo Sanchez
Pubblicato in: OpenMP: Enabling Massive Node-Level Parallelism - 17th International Workshop on OpenMP, IWOMP 2021, Bristol, UK, September 14–16, 2021, Proceedings, Numero 12870, 2021, Pagina/e 170-182, ISBN 978-3-030-85261-0
Editore: Springer International Publishing
DOI: 10.1007/978-3-030-85262-7_12

Self-adaptive K8S Cloud Controller for Time-sensitive Applications

Autori: Lubomir Bulej, Tomas Bures, Petr Hnetynka, Danylo Khalyeyev
Pubblicato in: 2021 47th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 2021, Pagina/e 166-169, ISBN 978-1-6654-2705-0
Editore: IEEE
DOI: 10.1109/seaa53835.2021.00029

Unified OpenCL Integration Methodology for FPGA Designs

Autori: Topi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen
Pubblicato in: IEEE Nordic Circuits and Systems Conference, 2021
Editore: IEEE

Cost-optimized TSN platform for aerospace applications based on RTEMS OS

Autori: Jorge Sánchez Garrido Luis Medina Valdés Rafael Rodríguez Gómez Javier Díaz
Pubblicato in: TSN Applications Conference, 2020
Editore: WEKA-FACHMEDIEN-EVENTS

Interface Modeling for Quality and Resource Management

Autori: M. Hendriks, M. Geilen, K. Goossens, R. de Jong, T. Basten
Pubblicato in: Logical Methods in Computer Science, LMCS 17(2), Numero Volume 17, Numero 2, 2021, ISSN 1860-5974
Editore: Technischen Universitat Braunschweig
DOI: 10.23638/lmcs-17(2:19)2021

Reconfigurable cyber-physical system for critical infrastructure protection in smart cities via smart video-surveillance

Autori: Juan Isern, Francisco Barranco, Daniel Deniz, Juho Lesonen, Jari Hannuksela, Richard R. Carrillo
Pubblicato in: Pattern Recognition Letters, Numero 140, 2020, Pagina/e 303-309, ISSN 0167-8655
Editore: Elsevier BV
DOI: 10.1016/j.patrec.2020.11.004

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments

Autori: Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá-Vayá
Pubblicato in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Numero 11733, 2019, Pagina/e 3-17, ISSN 1573-7640
Editore: Springer
DOI: 10.1007/978-3-030-27562-4_1

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Autori: Francesco Ratto, Tiziana Fanni, Luigi Raffo and Carlo Sau
Pubblicato in: Electronics 10 (1), 2021, ISSN 2079-9292
Editore: MDPI
DOI: 10.3390/electronics10010073

SMT-Based Consistency Checking of Configuration-Based Components Specifications

Autori: Laura Pandolfo, Luca Pulina, Simone Vuotto
Pubblicato in: IEEE Access, Numero 9, 2021, Pagina/e 83718-83726, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2021.3085911

Joint direct estimation of 3D geometry and 3D motion using spatio temporal gradients

Autori: Francisco Barranco, Cornelia Fermüller, Yiannis Aloimonos, Eduardo Ros
Pubblicato in: Pattern Recognition, 2020, Pagina/e 107759, ISSN 0031-3203
Editore: Pergamon Press
DOI: 10.1016/j.patcog.2020.107759

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Autori: Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Pubblicato in: Journal of Signal Processing Systems, Numero 93/5, 2021, Pagina/e 565-586, ISSN 1939-8018
Editore: Springer Verlag
DOI: 10.1007/s11265-021-01650-6

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Autori: Carlo Sau, Tiziana Fanni, Claudio Rubattu, Luigi Raffo, Francesca Palumbo
Pubblicato in: Microprocessors and Microsystems, Numero 80, 2021, Pagina/e 103326, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2020.103326

Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory

Autori: Joonas Iisakki Multanen, Kari Hepola, Asif Ali Khan, Jeronimo Castrillon, Pekka Jaaskelainen
Pubblicato in: IEEE Transactions on Computers, 2021, Pagina/e 1-1, ISSN 0018-9340
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2021.3117439

EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation

Autori: Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Santti, Lauri Koskinen
Pubblicato in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Numero 29/6, 2021, Pagina/e 1061-1072, ISSN 1063-8210
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tvlsi.2021.3070687

An early-stage statement-level metric for energy characterization of embedded processors

Autori: Vittoriano Muttillo, Paolo Giammatteo, Vincenzo Stoico, Luigi Pomante
Pubblicato in: Microprocessors and Microsystems, Numero 77, 2020, Pagina/e 103200, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2020.103200

An integrated hardware/software design methodology for signal processing systems

Autori: Lin Li, Carlo Sau, Tiziana Fanni, Jingui Li, Timo Viitanen, François Christophe, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala, Shuvra S. Bhattacharyya
Pubblicato in: Journal of Systems Architecture, Numero 93, 2019, Pagina/e 1-19, ISSN 1383-7621
Editore: Elsevier BV
DOI: 10.1016/j.sysarc.2018.12.010

Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction

Autori: Matias Koskela, Kalle Immonen, Markku Mäkitalo, Alessandro Foi, Timo Viitanen, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala
Pubblicato in: ACM Transactions on Graphics, Numero 38/5, 2019, Pagina/e 1-14, ISSN 0730-0301
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3269978

Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding

Autori: Carlo Sau, Dario Ligas, Tiziana Fanni, Luigi Raffo, Francesca Palumbo
Pubblicato in: IEEE Access, Numero 7, 2019, Pagina/e 153258-153268, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2019.2946054

A scenario- and platform-aware design flow for image-based control systems

Autori: Sajid Mohamed, Dip Goswami, Vishak Nathan, Raghu Rajappa, Twan Basten
Pubblicato in: Microprocessors and Microsystems, Numero 75, 2020, Pagina/e 103037, ISSN 0141-9331
Editore: Elsevier BV
DOI: 10.1016/j.micpro.2020.103037

Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Autori: Giacomo Valente, Tania Di Mascio, Gabriella DrAndrea, Luigi Pomante
Pubblicato in: IEEE Embedded Systems Letters, 2020, Pagina/e 1-1, ISSN 1943-0663
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/les.2020.3004302

Approximation-Aware Design of an Image-Based Control System

Autori: Sayandip De, Sajid Mohamed, Dip Goswami, Henk Corporaal
Pubblicato in: IEEE Access, Numero 8, 2020, Pagina/e 174568-174586, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3023047

Tydi: An Open Specification for Complex Data Structures Over Hardware Streams

Autori: Johan Peltenburg, Jeroen Van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
Pubblicato in: IEEE Micro, Numero 40/4, 2020, Pagina/e 120-130, ISSN 0272-1732
Editore: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2020.2996373

Managing latency in edge–cloud environment

Autori: Lubomír Bulej, Tomáš Bureš, Adam Filandr, Petr Hnětynka, Iveta Hnětynková, Jan Pacovský, Gabor Sandor, Ilias Gerostathopoulos
Pubblicato in: Journal of Systems and Software, Numero 172, 2021, Pagina/e 110872, ISSN 0164-1212
Editore: Elsevier BV
DOI: 10.1016/j.jss.2020.110872

Optimising Multiprocessor Image-Based Control Through Pipelining and Parallelism

Autori: Sajid Mohamed, Dip Goswami, Sayandip De, Twan Basten
Pubblicato in: IEEE Access, Numero 9, 2021, Pagina/e 112332-112358, ISSN 2169-3536
Editore: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2021.3103051

DTRiMC tool for TE0726-03M board

Autori: Kadlec Jiri, Likhonina Raissa
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

Full HD 60 FPS License plate detector for Zynq platform

Autori: Musil Petr, Juránek Roman, Zemčík Pavel
Pubblicato in: Brno University of Technology, 2019
Editore: Brno University of Technology

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project

Autori: Luigi Pomante, Francesca Palumbo, Claudia Rinaldi, Giacomo Valente, Carlo Sau, Tiziana Fanni, Frank van der Linden, Twan Basten, Marc Geilen, Geran Peeren, Jiri Kadlec, Pekka Jaaskelainen, Marcos Martinez, Jukka Saarinen, Tero Santti, Maria Katiuscia Zedda, Victor Sanchez, Dip Goswami, Zaid Al-Ars, Ad de Beer
Pubblicato in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Pagina/e 378-385, ISBN 978-1-7281-9535-3
Editore: IEEE
DOI: 10.1109/dsd51259.2020.00067

DDISH-GI: Dynamic Distributed Spherical Harmonics Global Illumination

Autori: Julius Ikkala, Petrus Kivi, Joel Alanko, Markku Mäkitalo and Pekka Jääskeläinen
Pubblicato in: Computer Graphics International, 2021
Editore: Computer Graphics International

FP01x8 Accelerator on TE0726-03M

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Pubblicato in: 2019
Editore: UTIA AV CR, v.v.i.

Lightweight profiler for embedded systems

Autori: Musil Petr, Juránek Roman, Zemčík Pavel
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

Waldboost package for Python

Autori: Roman Juranek
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency

Autori: Joonas Multanen, Kari Hepola, Pekka Jaaskelainen
Pubblicato in: 2020 IEEE 38th International Conference on Computer Design (ICCD), 2020, Pagina/e 356-363, ISBN 978-1-7281-9710-4
Editore: IEEE
DOI: 10.1109/iccd50377.2020.00066

Performing Electromagnetic Side-channel Attack On A Commercial AES-256 Device

Autori: Mika Kaustinen, Ohto Myllynen, Tero Jokela, Lauri Koskinen, Olli Heimo and Tero Säntti
Pubblicato in: Technical Report, 2021, ISBN 978-951-29-8653-8
Editore: University of Turku

DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board

Autori: Kadlec Jiri, Likhonina Raissa
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

Probabilistic Pose Estimation from Multiple Hypotheses

Autori: Escrivá, David & Perez-Jimenez, Alberto & Pérez Soler, Javier & Del Tejo Catalá, Omar & Perez-Cortes, Juan-Carlos & Guardiola, Jose-Luis.
Pubblicato in: 2021
Editore: N/A
DOI: 10.13140/rg.2.2.21609.21609

HDR merging and deghosting firmware

Autori: Musil Martin, Nosko Svetozár
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

Design Time and Run Time Resources for the ZynqBerry Board TE0726-03M with SDSoC 2018.2 Support

Autori: Kadlec, Jiri; Pohl, Zdenek; Kohout, Lukas
Pubblicato in: UTIA in FitOptiVis, 2019
Editore: UTIA AV CR, v.v.i.

Live Canny Edge Detection Demo for TE0808+TEBF0808 Trenz Board

Autori: Pohl, Zdenek; Kohout, Lukas; Kadlec, Jiri
Pubblicato in: UTIA in FitOptiVis, 2018
Editore: UTIA AV CR, v.v.i.

Design Time and Run Time Resources for Zynq Ultrascale+ TE0820-03-4EV-1E with SDSoC 2018.2 Support

Autori: Kadlec, Jiri; Pohl, Zdenek; Kohout, Lukas
Pubblicato in: UTIA in FitOptiVis, 2019
Editore: UTIA AV CR, v.v.i.

Stereo Demo

Autori: Pohl, Zdenek; Kohout, Lukas; Kadlec, Jiri
Pubblicato in: UTIA in FitOptiVis, 2018
Editore: UTIA AV CR, v.v.i.

Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module

Autori: Kohout, Lukas; Kadlec, Jiri; Pohl, Zdenek
Pubblicato in: UTIA in FitOptiVis, 2019
Editore: UTIA AV CR, v.v.i.

Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module

Autori: Kohout, Lukas; Kadlec, Jiri; Pohl, Zdenek
Pubblicato in: UTIA in FitOptiVis, 2019
Editore: UTIA AV CR, v.v.i.

Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support

Autori: Kadlec, Jiri;, Pohl, Zdenek; Kohout, Lukas
Pubblicato in: UTIA in FitOptiVis, 2019
Editore: UTIA AV CR, v.v.i.

AN AUTONOMIC MANAGER FOR EDGE-COMPUTING PLATFORMS

Autori: Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente
Pubblicato in: 2019
Editore: DATE

HDR Tonemapping demo

Autori: Martin Musil, Svetozar Nosko
Pubblicato in: 2019
Editore: BUT

HDR deghosting demo

Autori: Martin Musil, Petr Musil
Pubblicato in: 2019
Editore: BUT

FPGA object detection demo

Autori: Petr Musil, Roman Juranek
Pubblicato in: 2019
Editore: BUT

HEPSYCODE-MC: ELECTRONIC SYSTEM-LEVEL METHODOLOGY FOR HW/SW CO-DESIGN OF MIXED-CRITICALITY EMBEDDED SYSTEMS

Autori: Luigi Pomante, Vittoriano Muttillo, Marco Santic and Emilio Incerto
Pubblicato in: Conference on Design and Test Automation in Europe (DATE), 2019
Editore: DATE

ESL HW/SW Co-Design Methodology for Mixed-Criticality and Real-Time Embedded Systems

Autori: Vittoriano Muttillo
Pubblicato in: Conference on Design and Test Automation in Europe (DATE), 2019
Editore: DATE

Tutorial HEPSYCODE PhD Course

Autori: Vittoriano Muttillo, Luigi Pomante
Pubblicato in: Seminar at Università degli Studi dell'Aquila, 2019
Editore: Università degli Studi dell'Aquila

MECO AN INNOVATIVE RUN-TIME MANAGER TO EVALUATE THE DYNAMIC PARTIAL RECONFIGURATION PROFITABILITY

Autori: Gabriella D'Andrea
Pubblicato in: CWWMCA19 - Career Workshop for Women & Minorities in Computer Architecture, 2019
Editore: CWWMCA19

Design space exploration for hypervisor-based mixed-criticality systems

Autori: V. Muttillo, L. Pomante
Pubblicato in: CPS&IoT’2019 Summer School on Cyber-Physical Systems and Internet-of-Things, 2019
Editore: CPS&IoT’2019

JOINTER JOining flexIble moNitors wiTh hEterogeneous architectuRes

Autori: G. Valente, T. Fanni, C. Sau, C. Rubattu, F. Palumbo, L. Pomante
Pubblicato in: DATE2020 Design, Automation and Test in Europe Conference, 2020
Editore: DATE

Data Movers in DTRiMC tool for TE0726 03M 07S board

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas, Likhonina Raissa
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime

Autori: Jan Solanti, Michal Babej, Julius Ikkala, Vinod Kumar Malamal Vadakital, Pekka Jääskeläinen
Pubblicato in: Embedded Computer Systems: Architectures, MOdeling, and Simulation 21, 2021
Editore: OPENAIRE
DOI: 10.5281/zenodo.5091763

ACF object detector for FPGA

Autori: Musil Petr, Juránek Roman, Zemčík Pavel
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

Computer Vision on the edge to reduce network bandwidth and computing resources in multi-view 3D industrial inspection without hidden surfaces. (in review)

Autori: David Millán Escrivá, Javier Perez Soler, Jose Luis Guardiola, Juan Carlos Pérez Cortés.
Pubblicato in: Microprocessors and Microsystems, 2022, ISSN 0141-9331
Editore: Elsevier BV

A Composable Monitoring System for Heterogeneous Embedded Platforms

Autori: Giacomo Valente, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, Francesca Palumbo
Pubblicato in: ACM Transactions on Embedded Computing Systems, Numero 20/5, 2021, Pagina/e 1-34, ISSN 1539-9087
Editore: Association for Computing Machinary, Inc.
DOI: 10.1145/3461647

Radar Signal Processing and Fusion of Information

Autori: Reich Bořek
Pubblicato in: Brno University of Technology, 2020
Editore: Brno University of Technology

Two serial connected evaluation versions of FP03x8 accelerators for TE0820-03-4EV-1E module on TE0701-06 carrier board

Autori: Kadlec Jiri, Pohl Zdenek, Kohout Lukas
Pubblicato in: 2019
Editore: UTIA AV CR, v.v.i.

Hardware acceleration of object detection in images

Autori: Petr Musil
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

Diseño de un sistema de reconocimiento automático de comportamientos humanos basado en vídeo mediante redes neuronales recurrentes / Design of human activity recognition engine based on video analisis with Recurrent Neural Networks

Autori: Javier W. Ortiz Canepa
Pubblicato in: 2021, Pagina/e 0-71
Editore: Universidad Politécnica de Madrid

Ensuring Precision of Stereo Image Processing

Autori: Kuník Oliver
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

Ghost-free HDR video using FPGA

Autori: Martin Musil
Pubblicato in: Brno University of Technology, 2021
Editore: Brno University of Technology

Eight FP03x8 accelerators for TE0808-09-EG-ES1 module on TEBF0808 carrier board

Autori: Kadlec Jiri
Pubblicato in: 2021
Editore: UTIA AV CR, v.v.i.

Classification of Varying-Size Plankton Images with Convolutional Neural Network

Autori: Bureš Jaroslav
Pubblicato in: Brno University of Technology, 2020
Editore: Brno University of Technology

Methods for Efficient Integration of FPGA Accelerators with Big Data Systems

Autori: J.W. Peltenburg
Pubblicato in: 2020, ISBN 978-94-6366-333-5
Editore: Delft University of Technology
DOI: 10.4233/uuid:51989f8f-f672-4f4b-a059-86233869ff47

Reconfigurable and approximate computing for video coding

Autori: Francesca Palumbo, Carlo Sau
Pubblicato in: VLSI Architectures for Future Video Coding, 2019
Editore: Institution of Engineering and Technology

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