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Technology Advances for Pilotline of Enhanced Semiconductors for 3nm

Periodic Reporting for period 1 - TAPES3 (Technology Advances for Pilotline of Enhanced Semiconductors for 3nm)

Reporting period: 2018-10-01 to 2019-09-30

The overall objective of the TAPES3 project is to enable continuation of Moore’s law in line with the worldwide industry roadmap. Focus is on exploring and preparing innovations required to bring the industry’s capability in lithography, metrology, mask infrastructure and process modules to the levels required for creating products in the 3nm node.
In lithography the aim is to develop modules of a Hyper NA EUV systems with a 40% resolution improvement, a productivity of 185Wph and a modular design.
In Metrology the objective is enable the resolution and sensitivity required for metrology and process control of high aspect ratio gate all around (GAA) stacked features in 3nm CMOS devices.
In EUV mask infrastructure the aim is to assure availability of an EUV mask infrastructure capable to support lithography for the 3nm node with stable performance.
In process module exploration the objective is to find 3nm process modules demonstrating the ultimate capability of the traditional scaling and the potential of innovative solutions in patterning, design, device and integration to achieve 3nm technology figure of merit in terms of performance, power, area & cost (PPAC).
In Lithography design work by ASML on the sensor systems and wafer cooling started. Zeiss primarily focused on making available the mirror modules for the Projection Optical Box (POB). Realization of the mirror bodies and integration equipment has progressed, see Figure 1. DEMCON and ASML defined the Hyper-NA positioning module qualification tool. IMS Chips defined the Diffractive Optical Elements (DOEs) that are needed for measuring the mirrors and started their development. Fraunhofer IISB studied 3D mask effects the capability of their imaging and lithography modeling simulator - DrLiTHO. Fraunhofer IWS performed polishing experiments on optical materials with a dual ion beam source deposition system, see Figure 2. VDL defined the wafer handler systems and the requirements for the vacuum pre-aligner module and progressed on the analysis and control of contamination.
In Metrology the partners initiate development and assessment of the 3nm technology node metrology tools and hybrid methodologies. AMIL started the development of the new Critical Dimension Scan Electron Microscope, see Figure 3, with a high-resolution column prototype and assessed technology requirements and gaps. Nova started to investigate options for the improvements of their next generation Optical Critical Dimension OCD tool’s channel of information. FEI designed the new TEM platform and has realized a first prototype for initial tests and design verifications. KTI performed overlay system design readiness assessment including an optical simulation tool for overlay target designs. A Design of Experiment for a combined metrology and defectivity study for the 3nm technology node was established and a sampling plan to obtain 3nm relevant samples from the Pilot line was setup by the partners.

In the EUV mask infrastructure part of the project deposition of novel absorber materials is being evaluated. The individual capabilities of the partners were optimized and applied to verify the; film’s composition, optical properties, repairability and cleanability. Patterning evaluation of new material systems started. The supporting simulation work for the high NA anamorphic EUV system revealed that “effective extinction” of light is key, either obtained by alloying materials or by multilayering. In preparation of anamorphic and isomorphic mix-and-match imaging, overlay tuning of EUV reticles on Zeiss’ Fortune tool is under preparation. Reticle storage and lifetime are being studied by correlating experimental results obtained on TNO’s EBL2 and imec’s ASML EUV scanners. PTB contributes to this study with actinic metrology. Zeiss and PSI demonstrated resolution improvements for respectively defect repair and actinic inspection.

The process options assessment for the 3nm node focussed on 4 key tasks. EUV multi-patterning combined with self-aligned patterning schemes was identified as preferred patterning option. Gate All Around Nanosheet combined with Buried Power Rail integration was identified as the target device meeting 3nm node PPAC requirements. FEOL module development yielded: 1) a novel inner spacer module based on SiGeOx for gate capacitance reduction and 2) new Work Function Metal (WFM) stack fitting aggressive nanosheet spacing, see Figure 5, boosting power and performance. For the BEOL, Ru-based metallization solutions for interconnect resistance reduction and module development for semi-damascene integration based on subtractive Ru patterning have been developed, see Figure 6.
All developments in this project are geared to move the capability of the industry to produce high performance semiconductor ICs beyond the present state of the art, in fact enabling the Semiconductor Industry to migrate to the next technology node following Moore’s law.

In Lithography it is the migration from high NA (0.33) to Hyper NA (0.55) introduction of local wafer cooling, novel imaging sensors with a 10x performance improvement and new wafer stage with 2x acceleration. The associated positioning module and its qualification tool from DEMCON are one of a kind. The Hyper NA POB and its submodules exceed the state of the art by 2x in size, 2x in accuracy and complexity of the mirror surface. Also the DOEs for the Hyper NA optics have much tighter specifications.
To model 3-dimensional mask effects, analyze polychromatic effects and identify critical performance drivers Fraunhofer IISB is extending its imaging and lithography modeling simulator. New polishing techniques in which Ion beam smoothing using energetic ion bombardment of the surface to be polished is studied by Fraunhofer IWS.
For the new vacuum pre-aligner module for the wafer-handler being developed by VDL-ETG active contamination control beyond the current state of the art is needed.
In metrology, AMIL is developing next generation tools for measuring critical dimensions and new capabilities for high resolution analysis of high aspect ratio device structures. NOVA works on adding a unique channel of information to its current generation OCD tool to extract new type of information through the use of temporal changes in the spectra.
FEI develops a new generation Scanning Transmission Electron Microscopy (STEM) tool capable of reference metrology for ultra-thin and beam-sensitive layers in a near-line industrial environment. KLA is automating the OVL (overlay) methodology for the assessment of ‘on product overlay’.
In the EUV mask infrastructure of the project, one clearly innovative learning has been the correlation found between EBL2 and NXE wafer printing results, showing that mask storage contributes strongly to stable reticle performance in EUV-based imaging.
Regarding the process options assessment for 3nm technology during the 1st year of the TAPES3 project the consortium members progressed beyond the state of the art in the various fields: innovative patterning solutions for self-aligned EUV multi-patterning, Buried Power Rail (BPR) integration accommodating for desired logic cell area shrinking, module development for enhanced power and performance for Gate All Around Nanosheet (GAA NS) the 3nm node target device, solutions for low resistance BEOL interconnect based on Ru-metallization both for conventional and semi damascene integration.