The past 10 years have witnessed an explosion of the amount of visual information that must be transmitted and stored efficiently using limited and expensive resources. Advanced video coding that allows orders of magnitude reduction in the required bit-rates is regarded as an enabling technology to move personal communications to a higher level of interactivity. Common features required in personal communication systems are the need for high-quality, low bit-rate video coding implemented in high-performance, low energy consumption and low design complexity hardware platforms. This work aims to research novel embedded CPU architectures that will enable the acceleration of video coding applications in wireless networks by studying the feasibility of a vector multiprocessor architecture. The combination of several vector units running different threads of the same codec has significant potential in achieving leading area/power/cost metrics in real-time video-encoding. Vector Multiprocessing hardware is expected to enable the transmission of high-quality low-bit rate video content in current and next-generation networks and will contribute to make video content transmission as inconspicuous as voice transmission is today. The following clear objectives apply to this research: 1.Evaluation of the amount of data-level and thread-level parallelism in current and emerging video coding standards and specification of a suitable vector ISA for the proposed workloads. 2. Investigation of the micro-architectural parameters for the optimal multimedia vector pipeline coupled to a controlling CPU. 3. Investigations into the memory subsystem, processor interconnection and the specialization of the vector pipeline to support the algorithm threads in the multiprocessor platform. 4. Implementation of the vector multiprocessor SoC using a state of the art ASIC or equivalent FPGA technology.
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