Final Activity Report Summary - VECTORMULTIPROCESSOR (Vector Multiprocessor architecture for multimedia energy-efficient applications)
This work investigated the suitability of a vector coprocessor tightly coupled to a reconfigurable scalar core as an optimal platform to support high performance video coding.
After a thorough review of state of the art hardware architectures for video coding, the research analysed the computational demands of the latest standard for advanced video coding, namely the H.264 AVC algorithm which was also known as MPEG4 part 10. The STMicroelectronics implementation of H.264 was ported to the STxP70 scalar reconfigurable processor and its instruction set extended to target video coding applications. A complete vector instruction set architecture (ISA) and vector microarchitecture were proposed as generic high-performance extensions for scalar processors and their benefits were evaluated using cycle accurate architectural simulators. A dedicated accelerator was then proposed to target the complex task of arithmetic entropy coding in H.264 which proved not to be well suited for the data level parallelism exploited by vector architectures. The flexibility of the STxP70 core enabled this option as long as the hardware extensions, either vector or dedicated, were mapped to a reconfigurable fabric which could change its functionality depending on the loaded bitstream. The combination of reconfigurable processor and fabric formed the fundamental processing element with excellent scalable properties.
Finally, a proposal of how an array of these high-performance processing elements could be connected together was made in the form of a network-on-chip implementation that should provide the multiprocessing capabilities needed in current and future high-definition video products.
After a thorough review of state of the art hardware architectures for video coding, the research analysed the computational demands of the latest standard for advanced video coding, namely the H.264 AVC algorithm which was also known as MPEG4 part 10. The STMicroelectronics implementation of H.264 was ported to the STxP70 scalar reconfigurable processor and its instruction set extended to target video coding applications. A complete vector instruction set architecture (ISA) and vector microarchitecture were proposed as generic high-performance extensions for scalar processors and their benefits were evaluated using cycle accurate architectural simulators. A dedicated accelerator was then proposed to target the complex task of arithmetic entropy coding in H.264 which proved not to be well suited for the data level parallelism exploited by vector architectures. The flexibility of the STxP70 core enabled this option as long as the hardware extensions, either vector or dedicated, were mapped to a reconfigurable fabric which could change its functionality depending on the loaded bitstream. The combination of reconfigurable processor and fabric formed the fundamental processing element with excellent scalable properties.
Finally, a proposal of how an array of these high-performance processing elements could be connected together was made in the form of a network-on-chip implementation that should provide the multiprocessing capabilities needed in current and future high-definition video products.