Periodic Reporting for period 1 - PALMERA (Low Power and Fault Tolerant Cache Memory Design through a Combination of Hardware and Software Approaches)
Période du rapport: 2019-05-01 au 2021-04-30
Electronic circuits, such as microprocessors, are today used in all types of environments, including space and locations on earth where they are exposed to radiation. We then risk that high energy particles enter the circuit and cause a malfunction, possibly with critical outcome for a satellite or other equipment that the microprocessor controls. The memory of a microprocessor is particularly vulnerable, since a change to a stored value will be remembered and is not simply an instantaneous event.
Another major challenge for modern electronic circuits is their power consumption. This is the case from the smallest sensor node, running on, e.g. solar energy harvesting or irreplaceable coin cell batteries, through cell phones needing recharge frequently, to large data centres, where both the electricity bill and the heating of the microprocessors themselves are problems. One approach to save power is to reduce the supply voltage of the circuit. A consequence of this is reduced performance, however. A possible solution is to perform dynamic adaptation while the system is running in accordance with the current requirements of the system.
The goal of the PALMERA project is to design a low power and fault tolerant microprocessor memory through a combination of hardware and software approaches. We will develop circuit level solutions where each memory cell is made robust against radiation strikes. How much energy from a particle the memory can tolerate, is however dependent on its supply voltage. We will therefore control the circuit level solution with software that detects the current radiation status. It adapts the supply voltage so that we save power when no high energy particles are hitting the memory, thus saving power, and increase the supply voltage when high radiation tolerance is required.
Another major challenge for modern electronic circuits is their power consumption. This is the case from the smallest sensor node, running on, e.g. solar energy harvesting or irreplaceable coin cell batteries, through cell phones needing recharge frequently, to large data centres, where both the electricity bill and the heating of the microprocessors themselves are problems. One approach to save power is to reduce the supply voltage of the circuit. A consequence of this is reduced performance, however. A possible solution is to perform dynamic adaptation while the system is running in accordance with the current requirements of the system.
The goal of the PALMERA project is to design a low power and fault tolerant microprocessor memory through a combination of hardware and software approaches. We will develop circuit level solutions where each memory cell is made robust against radiation strikes. How much energy from a particle the memory can tolerate, is however dependent on its supply voltage. We will therefore control the circuit level solution with software that detects the current radiation status. It adapts the supply voltage so that we save power when no high energy particles are hitting the memory, thus saving power, and increase the supply voltage when high radiation tolerance is required.
The project started with focus on circuit level techniques for memories robust against high energy particle strikes caused by radiation. Starting from an extensive study of the current state of the art, a new Static Random Access Memory (SRAM) cell was developed that tolerates higher energy levels for particles that hit any of the internal nodes of the cell. Through simulations it was also shown that the cell was faster and that it required less power to read from the memory, compared to cells with comparable tolerance. The cell, named Nwise, is the first radiation hardened memory cell implemented in 28 nm FD-SOI semiconductor technology. The work was presented and published at an international scientific conference (IEEE NorCAS) and presented at several internal and external workshops and seminars.
The first successful Nwise design was extended with a Pwise SRAM cell with a similarly high tolerance against particle strikes, while being optimized towards short write times and low write power consumption. This extended work also contained a much more detailed simulation for both the two developed cells and current state of the art cells, based on complete circuit layouts. Furthermore, it was shown that both Nwise and Pwise tolerate particle strikes at any combination of two nodes in the cell at the same time. This is not the case for other cells with high radiation tolerance and short read and write times / low read or write power consumption. The work was published in an international scientific journal (IEEE Access) and presented at internal and external seminars.
The final step of the project consists of integrating Nwise and Pwise based memories with a software controlled methodology for power supply adaptation. Through cooperation and discussions with relevant space industry and academic researchers, different scenarios for expected radiation levels were found. Solar activity can for instance strongly influence the probability of particle strikes. When the probability is high, the system increases the supply voltage to give the memory higher radiation tolerance. On the other hand, when the probability of strikes is low, the supply voltage can be reduced to save power. As part of the work, it was investigation in detail what particle energies the memory cells can tolerate at different supply voltage levels. The work will be presented and published at an international scientific conference.
The first successful Nwise design was extended with a Pwise SRAM cell with a similarly high tolerance against particle strikes, while being optimized towards short write times and low write power consumption. This extended work also contained a much more detailed simulation for both the two developed cells and current state of the art cells, based on complete circuit layouts. Furthermore, it was shown that both Nwise and Pwise tolerate particle strikes at any combination of two nodes in the cell at the same time. This is not the case for other cells with high radiation tolerance and short read and write times / low read or write power consumption. The work was published in an international scientific journal (IEEE Access) and presented at internal and external seminars.
The final step of the project consists of integrating Nwise and Pwise based memories with a software controlled methodology for power supply adaptation. Through cooperation and discussions with relevant space industry and academic researchers, different scenarios for expected radiation levels were found. Solar activity can for instance strongly influence the probability of particle strikes. When the probability is high, the system increases the supply voltage to give the memory higher radiation tolerance. On the other hand, when the probability of strikes is low, the supply voltage can be reduced to save power. As part of the work, it was investigation in detail what particle energies the memory cells can tolerate at different supply voltage levels. The work will be presented and published at an international scientific conference.
The results beyond the state of the art of the project is outlined above. With space industry companies and researchers considering using the new memory cells in their circuit designs, the project can have a major impact for instance in energy constrained satellite systems. One such example is miniature CubeSat satellites with very limited solar panel area in low earth orbits. Experience show that their operation is influenced by solar storms, which can cause erroneous behaviour. They typically use non-space graded circuits. Memories may then be a weak point since faults are stored over time. This is something a design based on Nwise and Pwise cells may solve, thus making such relatively inexpensive satellites safer to use in application areas such as rural communication and environmental surveillance.