The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing In-Memory Computing (IMC) solutions to the fore. However, in order to be widely adopted, IMC solutions must be easily up-scalable (towards large scale systems). It requires, from the technology stand-point to provide a high enough density (and thus a high memory capacity on-chip) and also from the circuit design perspective to tackle the limitations related to analogue computing, mainly in terms of Signal to Noise Ratio (SNR) and robustness to device variability.
To address these challenges, the project followed two main objectives, both targeted towards the development of ‘non-von Neumann’ computing systems:
• Memory device technology development
First, non-von Neumann computing systems call for a revolution in memory technologies, requiring innovative approaches that enhance tight integration of logic and memory devices. To provide an answer to this challenge, the My-CUBE project coupled the high-density capabilities provided by 3D monolithic-integration approaches with the high performance provided by non-volatile resistive random access memory (ReRAM) technologies. With this strategy, My-CUBE developed the base building block of an IMC computing platform able to downscale towards very dense systems.
• Applicative-oriented circuitry development
Second, non-von Neumann computing systems demand a revolution in the approaches to implementing computing in hardware, moving towards in-situ IMC information processing with analogue components. However, analogue components suffer from intrinsic non-idealities, i.e. undesirable effects, which may degrade the accuracy of computations. In response, the My-CUBE project developed specific circuitry with enhanced immunity to the imperfections of these analogue components. The My-CUBE project also proposed coupling this optimized circuitry with low-precision binarized neural network (BNN) algorithms. This type of neural network exploits binary weights and activations, alleviating memory requirements while preserving high accuracy and enhanced resilience to analogue noise and variability issues. With this strategy, CEA researchers developed an ultra-low power IMC accelerator for BNN inference on-chip hardware implementation.
In terms of dissemination, we published up to 5 papers in the IEEE VLSI Symposium and IEDM conferences since the beginning of the project. These workshop/conference are the most important one in the field of the Electron Devices community. Moreover, an article was recently issued in Nature Communications Engineering. These results open the way to a high-density 3D NOR Resistive-Random-Access-Memory, which is a new class of memory, especially suitable for on-chip Artificial Intelligence processing.
