Periodic Reporting for period 4 - MY-CUBE (3D integration of a logic/memory CUBE for In-Memory-Computing)
Période du rapport: 2023-10-01 au 2024-03-31
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items, as it is the case in the brain. Things may change with the emergence of three key enabling technologies: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. My-CUBE leverage them towards a functionality-enhanced system with a tight entangling of logic and memory.
Following a holistic approach from the system to the material, My-CUBE unique solution relies on a new class of nano-technology, mixing at the fine-grain level a high capacity of non-volatile resistive memory coupled with new junctionless nanowire transistors 3D-interconnected, to perform data-centric computations. This technology that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient European integrated circuits.
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items, as it is the case in the brain. Things may change with the emergence of three key enabling technologies: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. My-CUBE leverage them towards a functionality-enhanced system with a tight entangling of logic and memory.
Following a holistic approach from the system to the material, My-CUBE unique solution relies on a new class of nano-technology, mixing at the fine-grain level a high capacity of non-volatile resistive memory coupled with new junctionless nanowire transistors 3D-interconnected, to perform data-centric computations. This technology that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient European integrated circuits.
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing In-Memory Computing (IMC) solutions to the fore. However, in order to be widely adopted, IMC solutions must be easily up-scalable (towards large scale systems). It requires, from the technology stand-point to provide a high enough density (and thus a high memory capacity on-chip) and also from the circuit design perspective to tackle the limitations related to analogue computing, mainly in terms of Signal to Noise Ratio (SNR) and robustness to device variability.
To address these challenges, the project followed two main objectives, both targeted towards the development of ‘non-von Neumann’ computing systems:
• Memory device technology development
First, non-von Neumann computing systems call for a revolution in memory technologies, requiring innovative approaches that enhance tight integration of logic and memory devices. To provide an answer to this challenge, the My-CUBE project coupled the high-density capabilities provided by 3D monolithic-integration approaches with the high performance provided by non-volatile resistive random access memory (ReRAM) technologies. With this strategy, My-CUBE developed the base building block of an IMC computing platform able to downscale towards very dense systems.
• Applicative-oriented circuitry development
Second, non-von Neumann computing systems demand a revolution in the approaches to implementing computing in hardware, moving towards in-situ IMC information processing with analogue components. However, analogue components suffer from intrinsic non-idealities, i.e. undesirable effects, which may degrade the accuracy of computations. In response, the My-CUBE project developed specific circuitry with enhanced immunity to the imperfections of these analogue components. The My-CUBE project also proposed coupling this optimized circuitry with low-precision binarized neural network (BNN) algorithms. This type of neural network exploits binary weights and activations, alleviating memory requirements while preserving high accuracy and enhanced resilience to analogue noise and variability issues. With this strategy, CEA researchers developed an ultra-low power IMC accelerator for BNN inference on-chip hardware implementation.
In terms of dissemination, we published up to 5 papers in the IEEE VLSI Symposium and IEDM conferences since the beginning of the project. These workshop/conference are the most important one in the field of the Electron Devices community. Moreover, an article was recently issued in Nature Communications Engineering. These results open the way to a high-density 3D NOR Resistive-Random-Access-Memory, which is a new class of memory, especially suitable for on-chip Artificial Intelligence processing.
To address these challenges, the project followed two main objectives, both targeted towards the development of ‘non-von Neumann’ computing systems:
• Memory device technology development
First, non-von Neumann computing systems call for a revolution in memory technologies, requiring innovative approaches that enhance tight integration of logic and memory devices. To provide an answer to this challenge, the My-CUBE project coupled the high-density capabilities provided by 3D monolithic-integration approaches with the high performance provided by non-volatile resistive random access memory (ReRAM) technologies. With this strategy, My-CUBE developed the base building block of an IMC computing platform able to downscale towards very dense systems.
• Applicative-oriented circuitry development
Second, non-von Neumann computing systems demand a revolution in the approaches to implementing computing in hardware, moving towards in-situ IMC information processing with analogue components. However, analogue components suffer from intrinsic non-idealities, i.e. undesirable effects, which may degrade the accuracy of computations. In response, the My-CUBE project developed specific circuitry with enhanced immunity to the imperfections of these analogue components. The My-CUBE project also proposed coupling this optimized circuitry with low-precision binarized neural network (BNN) algorithms. This type of neural network exploits binary weights and activations, alleviating memory requirements while preserving high accuracy and enhanced resilience to analogue noise and variability issues. With this strategy, CEA researchers developed an ultra-low power IMC accelerator for BNN inference on-chip hardware implementation.
In terms of dissemination, we published up to 5 papers in the IEEE VLSI Symposium and IEDM conferences since the beginning of the project. These workshop/conference are the most important one in the field of the Electron Devices community. Moreover, an article was recently issued in Nature Communications Engineering. These results open the way to a high-density 3D NOR Resistive-Random-Access-Memory, which is a new class of memory, especially suitable for on-chip Artificial Intelligence processing.
The research carried out during My-CUBE delivered a number of results beyond the state-of-the-art:
• A compact one-transistor – one-resistor (1T1R) memory cell, where the ReRAM active material (HfO2) is deposited inside the transistor drain contact, has been demonstrated. This approach has successfully been implemented for both gate-all-around stacked nanosheet and 28nm fully depleted silicon-on-insulator (FDSOI) logic transistor technologies. Notably, this 1T1R architecture benefits from 3D integration scalability and the co-location of logic and memory, allowing to reach memory density capabilities that are competitive with crossbar ultra-dense architectures while preventing sneak-path current issues. Remarkably, >1E6 endurance cycles, 2h data retention at 150°C and >1E9 read disturb with multi-level cell (MLC) capabilities have been achieved, which is competitively with the state-of-the art.
• An IMC-oriented accelerator based on ReRAM-based two-transistor – two-resistor (2T2R) cells with a capacitive output neuron to implement low precision BNNs has been fabricated above CMOS technology, highlighting excellent robustness to noise and analogue variability. An excellent peak energy efficiency of 96 TOPS/W has been achieved while promising high BNN accuracy on image-classification tasks. Moreover, this solution promises a state-of-the-art 449.3 TOPS/W for an equivalent hardware implementation in 22nm FDSOI technology.
• In addition to the aforementioned neural network accelerators, other applications have been explored, from 3D NOR non-volatile-memory to high-performance computing, both exploiting the high-density integration flow developed in My-CUBE.
• A compact one-transistor – one-resistor (1T1R) memory cell, where the ReRAM active material (HfO2) is deposited inside the transistor drain contact, has been demonstrated. This approach has successfully been implemented for both gate-all-around stacked nanosheet and 28nm fully depleted silicon-on-insulator (FDSOI) logic transistor technologies. Notably, this 1T1R architecture benefits from 3D integration scalability and the co-location of logic and memory, allowing to reach memory density capabilities that are competitive with crossbar ultra-dense architectures while preventing sneak-path current issues. Remarkably, >1E6 endurance cycles, 2h data retention at 150°C and >1E9 read disturb with multi-level cell (MLC) capabilities have been achieved, which is competitively with the state-of-the art.
• An IMC-oriented accelerator based on ReRAM-based two-transistor – two-resistor (2T2R) cells with a capacitive output neuron to implement low precision BNNs has been fabricated above CMOS technology, highlighting excellent robustness to noise and analogue variability. An excellent peak energy efficiency of 96 TOPS/W has been achieved while promising high BNN accuracy on image-classification tasks. Moreover, this solution promises a state-of-the-art 449.3 TOPS/W for an equivalent hardware implementation in 22nm FDSOI technology.
• In addition to the aforementioned neural network accelerators, other applications have been explored, from 3D NOR non-volatile-memory to high-performance computing, both exploiting the high-density integration flow developed in My-CUBE.