Periodic Reporting for period 3 - MY-CUBE (3D integration of a logic/memory CUBE for In-Memory-Computing)
Reporting period: 2022-04-01 to 2023-09-30
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items, as it is the case in the brain. Things may change with the emergence of three key enabling technologies: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. My-CUBE will leverage them towards a functionality-enhanced system with a tight entangling of logic and memory.
Following a holistic approach from the system to the material, My-CUBE unique solution relies on a new class of nano-technology, mixing at the fine-grain level a high capacity of non-volatile resistive memory coupled with new junctionless nanowire transistors 3D-interconnected, to perform data-centric computations. This technology that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient European integrated circuits.
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items, as it is the case in the brain. Things may change with the emergence of three key enabling technologies: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. My-CUBE will leverage them towards a functionality-enhanced system with a tight entangling of logic and memory.
Following a holistic approach from the system to the material, My-CUBE unique solution relies on a new class of nano-technology, mixing at the fine-grain level a high capacity of non-volatile resistive memory coupled with new junctionless nanowire transistors 3D-interconnected, to perform data-centric computations. This technology that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient European integrated circuits.
The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing In-Memory Computing (IMC) solutions to the fore. Since large data set are usually stored in Non-Volatile Memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, whereas keeping the programming control provided by 1T1R bit-cell, we propose to combine Gate-All-Around stacked junctionless nanowires, and OxRAM technology to create a 3D memory pillar with ultra-high-density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on SPICE simulations, we demonstrated In-Memory-Computing scouting logic operations with up to three operands.
Moreover, we have proposed and demonstrated experimentally, on a fabricated hybrid CMOS-RRAM integrated circuit, a robust in-memory XOR operation based on a 2T 2R cell used in a resistive bridge manner. With this architecture, the RRAM read operation and the Binary-Neural-Network multiplication operation can be achieved simultaneously. Based on our measurements and extensive SPICE Monte Carlo simulations, we validate that this approach is suitable for large neurons with a low error rate. Based on the circuit simulation results, we highlight the resilience of this approach at the network level, with a excellent accuracy on the MNIST and CIFAR-10 datasets.
We published up to 5 papers in the IEEE VLSI Symposium and IEDM conferences since the beginning of the project. These workshop/conference are the most important one in the field of the Electron Devices community
Moreover, we have proposed and demonstrated experimentally, on a fabricated hybrid CMOS-RRAM integrated circuit, a robust in-memory XOR operation based on a 2T 2R cell used in a resistive bridge manner. With this architecture, the RRAM read operation and the Binary-Neural-Network multiplication operation can be achieved simultaneously. Based on our measurements and extensive SPICE Monte Carlo simulations, we validate that this approach is suitable for large neurons with a low error rate. Based on the circuit simulation results, we highlight the resilience of this approach at the network level, with a excellent accuracy on the MNIST and CIFAR-10 datasets.
We published up to 5 papers in the IEEE VLSI Symposium and IEDM conferences since the beginning of the project. These workshop/conference are the most important one in the field of the Electron Devices community
We have explored a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO2-based OxRAM with select junctionless transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. In this technology, we experimentally demonstrated scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach. We are currently exploring Binary Neural Networks on these technology including capacitance based neurons.
In the future, we will continue to study the scalability of this novel high-density 3D memory technology as well as its potential applications.
In the future, we will continue to study the scalability of this novel high-density 3D memory technology as well as its potential applications.