Exploitable results
The quality and development time of any electronic product depends greatly on the degree of simulation that can be performed during the design phase. Therefore, the power and efficiency of the simulator is of paramount importance. As a result of the AIDA project, which included research by ICL into powerful simulation algorithms and scheduling methods, ICL has developed an extremely powerful simulator for VHDL designs. Known as VISE, it provides the power and simulation performance required for real system level designs, providing approximately 10 times the performance of any other commercially available VHDL simulator at the register transfer language (RTL) level or above. This translates into the ability to achieve a greater amount of simulation in a given time, helping achieve the best design, first time and on time.
The simulation technology used in VISE includes unique optimization for higher levels of VHDL specification and highly efficient use of memory, allowing models of very large systems to be built without the need for extra hardware investment. Independent module compilation facilities and support for hierarchical design methods give a flexible but controlled approach to system development. VISE also incorporates a powerful visualization tool which provides a flexible, interactive environment for design verification.
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