The objective of this proof-of-concept project is the technical and market validation of a new analogue circuit for in-memory computing.
In-memory computing is a new trend in computing systems which can improve the energy efficiency and sustainability of computing with big data. Currently, all conventional computing systems are based on von Neumann architecture, where data are processed and stored in separate chips. The communication and transfer of these data is a major bottleneck for computation, named memory wall. In memory computing aims at overcoming this bottleneck by processing data in situ where they are stored, i.e. directly within the memory.
The circuits addressed in this project can solve algebra problems in crosspoint memory arrays. These array circuits have been shown to accelerate the matrix vector multiplication (MVM) in the analogue domain by applying a voltage vector V at the rows of the crosspoint array, where the matrix A is stored as the conductance G of resistive memory devices, such as resistive switching memory (RRAM) and phase change memory (PCM). The extracted current vector I from the array provides the solution to the problem I = AV. Our circuit goes one step further by enabling inverse MVM, i.e. providing the voltage vector V which, multiplied by the coefficient matrix A, yields the input current I, thus solving the linear system of equations AV = I, where V is the unknown. Similar to MVM, the inverse MVM is executed in just one step, without iteration. The circuit can similarly accelerate other linear algebra operations, such as eigenvector calculation and matrix inversion. Since linear algebra is at the backbone of most machine learning algorithms, the circuit is extremely promising for developing hardware accelerators of machine learning tools.
Within this project, we have developed a technical demonstration of this new circuit to support the technical feasibility of the concept. We have also performed a market analysis of hardware accelerators for machine learning, thus providing a market validation for our concept.
The results indicate that the circuit has O(1) complexity, namely the time to solve a given problem does not scale with the size of the matrix. Also, the energy efficiency might reach 100,000 TOps/W, which is about 2 orders of magnitude higher than the existing application specific integrated circuits (ASICs). The new concept can penetrate the market of AI hardware accelerators, which corresponds to a total addressable market (TAM) of 24.7 billion USD in 2025.
