Description du projet
Un nouveau plan de communication sans fil sur puce
Les futurs systèmes de communication sans fil et plateformes informatiques doivent afficher des débits de données beaucoup plus élevés, une flexibilité accrue et une efficacité énergétique nettement supérieure à celle des systèmes actuels. Étant donné que les processeurs hétérogènes sont largement disponibles, il est indispensable de mettre en place de nouvelles plateformes capables de tirer parti de cette énorme puissance de calcul. Pour assurer une efficacité proche de celle des circuits intégrés dédiés à des applications spécifiques (ASIC pour «application-specific integrated circuit») sans les coûts, le temps de développement ou les restrictions qui y sont associés, le projet WiPLASH, financé par l’UE, met au point un plan de communication sans fil sur puce afin d’assurer la plasticité architecturale, la reconfigurabilité et l’adaptation aux exigences de toutes les applications sans perte de généralité. Plus particulièrement, le projet va concevoir un prototype d’antenne en graphène miniaturisée et réglable dans la bande térahertz. Il permettra également de co-intégrer des composants de RF en graphène dans des émetteurs-récepteurs à ondes submillimétriques et de faire la démonstration de réseaux à l’échelle de la puce sans fil, reconfigurables et à faible consommation.
Objectif
The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.
In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.
Champ scientifique
- engineering and technologynanotechnologynano-materialstwo-dimensional nanostructuresgraphene
- engineering and technologyelectrical engineering, electronic engineering, information engineeringelectronic engineeringanalogue electronics
- natural sciencescomputer and information sciencesartificial intelligencemachine learningdeep learning
- engineering and technologyelectrical engineering, electronic engineering, information engineeringinformation engineeringtelecommunicationsradio technology
Mots‑clés
Programme(s)
Régime de financement
RIA - Research and Innovation actionCoordinateur
08034 Barcelona
Espagne