Periodic Reporting for period 1 - PlasmoniAC (Energy- and Size-efficient Ultra-fast Plasmonic Circuits for Neuromorphic Computing Architectures)
Período documentado: 2020-01-01 hasta 2021-06-30
Following a holistic hardware/software co-design approach, PlasmoniAC targets the following objectives:
i) to elevate plasmonics into a computationally-credible platform with Nx100 Gb/s bandwidth, μm2-scale size and >1014 MAC/s/W computational energy efficiency, using CMOS compatible BTO and SiOC materials for electro-and thermo-optic computational functions,
ii) to blend them via a powerful 3D co-integration platform with SixNy-based photonic interconnects and with non-volatile memristor-based weight control,
iii) to fabricate two different sets of 100 Gb/s 16-and 8-fan-in linear plasmonic neurons,
iv) to deploy a whole new class of plasmo-electronic and nanophotonic activation modules,
v) to demonstrate a full-set of sin2(x), ReLU, sigmoid and tanh plasmonic neurons for Feed-Forward and recurrent neurons,
vi) to embrace them into a properly adapted Deep Learning training model suite, ultimately delivering a neuromorphic plasmonic software design library, and
vii) to apply them on IT security-oriented applications for threat and malware detection.
i) to elevate plasmonics into a computationally-credible platform with Nx100 Gb/s bandwidth, μm2-scale size and >1014 MAC/s/W computational energy efficiency, using CMOS compatible BTO and SiOC materials for electro-and thermo-optic computational functions,
ii) to blend them via a powerful 3D co-integration platform with SixNy-based photonic interconnects and with non-volatile memristor-based weight control,
iii) to fabricate two different sets of 100 Gb/s 16-and 8-fan-in linear plasmonic neurons,
iv) to deploy a whole new class of plasmo-electronic and nanophotonic activation modules,
v) to demonstrate a full-set of sin2(x), ReLU, sigmoid and tanh plasmonic neurons for Feed-Forward and recurrent neurons,
vi) to embrace them into a properly adapted Deep Learning training model suite, ultimately delivering a neuromorphic plasmonic software design library, and
vii) to apply them on IT security-oriented applications for threat and malware detection.
Neuromorphic plasmonic hardware design, specification and training:System level models and specifications for the wavelength and phase encoded neurons of the project have been developed, taking into account hardware restrictions and margins of the envisaged technology. Noise- and electro-optical bandwidth-aware training methods have been investigated in parallel with the development of co-simulation environment interfacing VPI suite with Python and Deep Learning frameworks i.e. Pytorch to run, for the first time, over photonic circuit level simulation layouts. Application use cases have been extended beyond lookaside accelerators for DDoS attack recognition, including a) cloud based image recognition and classification tasks, and b) signal encoding/decoding for high-quality IM/DD optical transmission links. Finally, a 3D integration process-flow for linear plasmonic neurons was established merging BTO, SiOC, TiO2 and CMOS plasmonics on a SiN platform identifying all the required process steps starting from marker definition to memristor integration.
Materials and interconnect technology: Material properties for a-Si, BTO, SiOC and TiO2 have been exhaustively investigated elaborating on material composition, complex refractive index values and fabrication requirements laying the foreground for the subsequent development of plasmonic compute devices and respective waveguide interfaces on SiN. Passive silicon nitride building blocks for TE and TM polarization have been fabricated and tested including: grating couplers with coupling loss of 6-7 dB, 4 and 8 channel demultiplexers with channel spacing of 3.6,7.8 and 14.3 nm for both polarizations in C band. Measurements revealed also waveguide propagation losses of approximately 1 dB/cm for both polarizations.
Architectures and prototypes:In parallel, a series of pro-active actions have been enforced to accelerate the development of forerunner prototypes of PlasmoniAC linear neurons throughout a series of intermediate fabrication runs exploiting a) MPW-grade SiPho and b) >100GHz bandwidth POH based technologies. These prototypes have provided rapid and useful insight into the architectural and technological concepts pursued within PlasmoniAC, while contributing significantly to the compensation of delays imposed by Covid-19 and risk mitigation.
Non-linear activation function technology: Graphene PDs exploiting plasmonics on SiN have been designed and fabricated aiming at unbiased operation and ultra-large bandwidth > 100GHz. Marching ahead to InP-on-SiN structures and envisioned recurrent neuron architectures, two types of PhC nanocavity lasers have been designed and fabricated targeting at Q values higher than 105. When pumped in AC, at a repetition rate of 1MHz with pulse duration of 20 ns, laser emission was visible on many devices exhibiting lasing threshold values of 300μA. Micro-heaters with a tuning efficiency of 2.15 nm/mW have been also developed. TiA designs and electrical simulations have progressed significantly relying on fitted equivalent circuit models for the employed PD and modulator technologies.
Weighting technology: Memristive devices to be integrated in the PlasmoniAC demonstrators for the non-volatile weights have been also developed. Metal-insulator-metal type structures based on HfO2, as known from the state-of-the-art, were modified to improve the properties as analog memory elements. The integration of a metal-oxide layer enabled a more controlled exchange of oxygen vacancies and so less stochastic and more symmetric resistance tuning. Several device iterations were executed to optimize the characteristics. Finally, stand-alone plasmonic TiO2 based TO weighting devices resorting to asymmetric and ring assisted MZI layouts have been fabricated with respective simulations bearing promises for an ultra-low power consumption below 1mW inducing full pi phase shift and increased thermal isolation employing lateral waveguide trenches.
Experimental Validation of Linear Neuron prototypes: Experimental results on 4-fan in wavelength and phase encoded SiPho neuron prototypes revealed optical compute capabilities up to 32GMAC/sec/axon achieving accuracies of up to ~98% on optical inference for classification tasks using CIFAR10 and MNIST datasets. That demonstration attracted much attention by the scientific community receiving the second honourable mention in the “Corning Outstanding” student paper competition at OFC 2021, highlighting in this way the future-proof character and strong ambitions of the project.
Materials and interconnect technology: Material properties for a-Si, BTO, SiOC and TiO2 have been exhaustively investigated elaborating on material composition, complex refractive index values and fabrication requirements laying the foreground for the subsequent development of plasmonic compute devices and respective waveguide interfaces on SiN. Passive silicon nitride building blocks for TE and TM polarization have been fabricated and tested including: grating couplers with coupling loss of 6-7 dB, 4 and 8 channel demultiplexers with channel spacing of 3.6,7.8 and 14.3 nm for both polarizations in C band. Measurements revealed also waveguide propagation losses of approximately 1 dB/cm for both polarizations.
Architectures and prototypes:In parallel, a series of pro-active actions have been enforced to accelerate the development of forerunner prototypes of PlasmoniAC linear neurons throughout a series of intermediate fabrication runs exploiting a) MPW-grade SiPho and b) >100GHz bandwidth POH based technologies. These prototypes have provided rapid and useful insight into the architectural and technological concepts pursued within PlasmoniAC, while contributing significantly to the compensation of delays imposed by Covid-19 and risk mitigation.
Non-linear activation function technology: Graphene PDs exploiting plasmonics on SiN have been designed and fabricated aiming at unbiased operation and ultra-large bandwidth > 100GHz. Marching ahead to InP-on-SiN structures and envisioned recurrent neuron architectures, two types of PhC nanocavity lasers have been designed and fabricated targeting at Q values higher than 105. When pumped in AC, at a repetition rate of 1MHz with pulse duration of 20 ns, laser emission was visible on many devices exhibiting lasing threshold values of 300μA. Micro-heaters with a tuning efficiency of 2.15 nm/mW have been also developed. TiA designs and electrical simulations have progressed significantly relying on fitted equivalent circuit models for the employed PD and modulator technologies.
Weighting technology: Memristive devices to be integrated in the PlasmoniAC demonstrators for the non-volatile weights have been also developed. Metal-insulator-metal type structures based on HfO2, as known from the state-of-the-art, were modified to improve the properties as analog memory elements. The integration of a metal-oxide layer enabled a more controlled exchange of oxygen vacancies and so less stochastic and more symmetric resistance tuning. Several device iterations were executed to optimize the characteristics. Finally, stand-alone plasmonic TiO2 based TO weighting devices resorting to asymmetric and ring assisted MZI layouts have been fabricated with respective simulations bearing promises for an ultra-low power consumption below 1mW inducing full pi phase shift and increased thermal isolation employing lateral waveguide trenches.
Experimental Validation of Linear Neuron prototypes: Experimental results on 4-fan in wavelength and phase encoded SiPho neuron prototypes revealed optical compute capabilities up to 32GMAC/sec/axon achieving accuracies of up to ~98% on optical inference for classification tasks using CIFAR10 and MNIST datasets. That demonstration attracted much attention by the scientific community receiving the second honourable mention in the “Corning Outstanding” student paper competition at OFC 2021, highlighting in this way the future-proof character and strong ambitions of the project.
Adopting SixNy as its interconnect platform due to its low-loss waveguide and passive circuit functions, PlasmoniAC aims to fill the gap in the sparse landscape of SiN actives by transferring well-known plasmonic and nanophotonic schemes on the SixNy waveguide platform and turning it into a powerful and homogenized active device technology. In doing so, PlasmoniAC will deliver for the first time a complete suite of μm2-scale laser, modulator and PD devices on SixNy and will release for the first time on-chip data modulation and detection capabilities at 100Gb/s, significantly outperforming all state-of-the-art modules.Compared to both electronics and photonics, PlasmoniAC’s weight structures offer >1-3 orders of magnitude higher computational power vs area efficiency in MAC/s/cm2, while forming the lowest power solution compared to all photonic weight layouts requiring just 4-16% of the electrical power consumed by photonics. PlasmoniAC brings a neuron technology that bridges the best-possible technologies along its constituent functions, concluding to layouts that operate at 4-5 orders magnitude higher clock frequencies, 2-4 orders of magnitude higher computational footprint efficiencies and 1 order magnitude higher energy efficiency, unleashing a record-high computational power per neuron that is 2-3 orders of magnitude higher compared to electronics.