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CORDIS

SELENE: Self-monitored Dependable platform for High-Performance Safety-Critical Systems

Deliverables

Dissemination & Exploitation report for PPR2, plans for exploitation beyond end of project

A summary of the dissemination and exploitation actions undertaken during the project as well as an overview of the plans of partners to further exploit the generated knowledge beyond the project lifetime This include a plan of a joint book and inputs from T54

SELENE software platform description

Final hypervisor RTOS and AI user manual Safety concept T32 T35

Initial software setup guide

Preliminary hypervisor and RTOS user manual (T3.1 - T3.5).

Use case descriptions and requirements

Description of the space, robotics and railway use cases, and their requirements on the SELENE platform (T1.3).

Use case evaluation

List of evaluation criteria and requirements and an assessment report using quantitative and qualitative dataT45

Final hardware support for safety, security, virtualization and acceleration

Technical contributions by M30 T22 T25

Dissemination & Exploitation report for PPR1, plans for PPR2

The initial dissemination plan reports on the dissemination activities undertaken in the first reporting period, and provides detailed plan for the rest of the project for both dissemination and exploitation including result from T5.4.

Website, flyer, initial dissemination and exploitation plan

Communication and dissemination materials targeting a variety of stakeholders, as well as the project website, and a plan for early dissemination and exploitation.

Preliminary SELENE System-on-chip description and configuration guide

First version of the FPGA board user manual (T2.1 - T2.6).

Lessons learnt

Final report available to the public providing hindsight on project choices management and technical experience and future directions including observations from the advisory board

Preliminary hardware support for safety, security, virtualization and acceleration features

Technical contributions by M12 (T2.2 - T2.5).

Final SELENE System-on-chip description and configuration guide

Final FPGA board user manual T22 T26

Intermediate hardware support for safety, security, virtualization and acceleration features

Technical contributions by M18 (T2.2 - T2.5).

SELENE platform requirements and use constraints

Report collecting hardware and software SELENE platform requirements and use constraints (T1.1-T1.2).

Intermediate SELENE System-on-chip description and configuration guide

Updated FPGA board user manual (T2.1 - T2.6).

FPGA platform definition

Specification of the characteristics needed by the SoC in the FPGA board to use, FPGA board choice, and fault mitigation measures needed for space environments (T1.4).

Preliminary software architecture Initial software enabling on target platform

Technical solutions description, and source code and configurations of hypervisor and Linux (T3.1 - T3.5).

Preliminary software architecture

Initial software solutions architecture and Hypervisor and Linux/RTOS setup (T3.1 - T3.5)..

Publications

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems

Author(s): Carles Hernandez, Jose Flieh, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Ronnback, Johan Klockars, Nicholas McGuire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartet, Dierk Ludemann, Mikel Labayen
Published in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Page(s) 370-377, ISBN 978-1-7281-9535-3
Publisher: IEEE
DOI: 10.1109/dsd51259.2020.00066

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

Author(s): Francisco Bas, Sergi Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo GIL, Oriol Sala, Fabio Mazzocchetti, David Trilla,Jaume Abella
Published in: 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Publisher: IEEE

On the reliability of hardware event monitors in MPSoCs for critical domains

Author(s): Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Enrico Mezzetti, Jaume Abella, Mikel Fernandez, Guillem Bernat, Francisco J. Cazorla
Published in: Proceedings of the 35th Annual ACM Symposium on Applied Computing, 2020, Page(s) 580-589, ISBN 9781450368667
Publisher: ACM
DOI: 10.1145/3341105.3373955

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem

Author(s): Vatistas Kostalampros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó and Carles Hernandez
Published in: International Conference on Field-Programmable Logic and Applications (FPL), 2021
Publisher: IEEE

Improving the Robustness of Redundant Execution with Register File Randomization

Author(s): Ilya Tuzov, Pablo Andreu, Laura Medina, Tomas Picornell, Antonio Robles, Pedro Lopez, Jose Flich, Carles Hernández
Published in: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, Page(s) 1-9
Publisher: IEEE
DOI: 10.1109/iccad51958.2021.9643466

SafeSU-2: a Safe Statistics Unit for Space MPSoCs

Author(s): Guillem Cabo, Sergi Alcaide, Carles Hernandez, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella
Published in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Issue 1, 2022, Page(s) 1085-1086
Publisher: IEEE
DOI: 10.23919/date54114.2022.9774515

Empirical Analysis of the Specialization of a Diversity Metric per Circuit Path

Author(s): Sergi Alcaide, Carles Hernández, Jaume Abella
Published in: 17th Workshop on Silicon Errors in Logic - System Effects, 2021
Publisher: No oficial proceedings

Security, Reliability and Test Aspects of the RISC-V Ecosystem

Author(s): Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gurkaynak, Helena Handschuh, Carles Hernandez, Mike Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
Published in: 2021 IEEE European Test Symposium (ETS), 2021, Page(s) 1-10, ISBN 978-1-6654-1849-2
Publisher: IEEE
DOI: 10.1109/ets50041.2021.9465449

Cuotas hardware para el despliegue de aplicaciones de alta criticidad en sistemas multiprocesador

Author(s): Pablo Andreu Cerezo, Carles Hernández, Pedro Lopez
Published in: Actas de las Jornadas SARTECO 2022, Issue 1, 2022, ISBN 978-84-1302-185-0
Publisher: Universidad de Alicante

Enabling hardware randomization across the cache hierarchy in Linux-Class processors

Author(s): Doblas, Max; Kostalabros, Ioannis-Vatistas; Moreto Planas, Miquel; Hernández Luz, Carles
Published in: 4th Workshop on Computer Architecture Research with RISC-V, Issue 1, 2020
Publisher: No publisher

The SELENE Deep Learning Acceleration Framework for Safety-related Applications

Author(s): Laura Medina, Salvador Carrión, Pablo Andreu, Tomás Picornell, José Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alecis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess
Published in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Issue 1, 2022, Page(s) 636-639
Publisher: IEEE
DOI: 10.23919/date54114.2022.9774578

Artificial Intelligence for High-performance Human Space Flight Avionics Systems

Author(s): Carles Hernandez, Nick Hauptvogel, Laura Medina, Charles-Alexis Lefebvre, Jose Flich, Martin Rönnbäck, Dierk Lüdemann
Published in: Data Systems In Aerospace Conference (DASIA 2022), 2022
Publisher: Eurospace

SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores

Author(s): Francisco Bas, Pedro Benedicte, Sergi Alcaide, Guillem Cabo, Fabio Mazzocchetti and Jaume Abella
Published in: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Issue 1, 2022, Page(s) 358-363
Publisher: IEEE
DOI: 10.23919/date54114.2022.9774540

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation

Author(s): Oriol Sala, Sergi Alcaide, Jaume Abella, Guillem Cabo, Francisco Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Fabio Mazzocchetti, Guillermo Gil
Published in: 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Publisher: IEEE
DOI: 10.1109/iolts52814.2021.9486689

HLSinf: Una Plataforma de Aceleración de Procesos de Inferencia en FPGA aplicado a Imágenes Médicas

Author(s): Laura Medina, Izan Catalán, José Flich, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau y David Briand
Published in: Actas de las Jornadas SARTECO 2022, 2022, Page(s) 185-190, ISBN 978-84-1302-185-0
Publisher: Universidad de Alicante

Bounding inter-core interference with a hardware quota mechanism

Author(s): Pablo Andreu Cerezo; Carles Hernández; Pedro Lopez
Published in: 18th International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems (ACACES 2022), Issue 1, 2022, ISBN 978-88-947027-0-5
Publisher: HiPEAC, the European Network of Excellence on High Performance Embedded Architecture and Compilation

End-to-end QoS for the Open Source safety-relevant RISC-V SELENE platform

Author(s): Pablo Andreu, Carles Hernández, Tomas Picornell, Pedro Lopez, Sergi Alcaide, Francisco Bas, Pedro Benedicte, Guillem Cabo, Feng Chang, Francisco Fuentes, Jaume Abella
Published in: Issue 1, 2022
Publisher: arxiv.org

The HLSinf AI hardware accelerator for Safety-related Applications in SELENE

Author(s): Laura Medina, José Flich, Carles Hernández
Published in: 18th International Summer School on Advanced Computer Architecture and Compilation for High-performance Embedded Systems (ACACES 2022), Issue 1, 2022, Page(s) 109-112, ISBN 978-88-947027-0-5
Publisher: HiPEAC, the European Network of Excellence on High Performance Embedded Architecture and Compilation

Static Hardware Partitioning on RISC-V: Shortcomings, Limitations and Prospects

Author(s): Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Maurer
Published in: 2022
Publisher: arxiv.org

Development of a Light Weight L2-Cache Controller

Author(s): Måns Arildsson
Published in: 2022
Publisher: Luleå University of Technology

Design and Implementation of a Network-on-Chip based Embedded System-on-Chip

Author(s): Panagiotis Strikos
Published in: 2021
Publisher: Chalmers University of Technology

Measuring and Controlling Multicore Contention in a RISC-V System-on-Chip

Author(s): Pablo Andreu
Published in: 2021
Publisher: Universitat Politècnica de València

Design of a diversity enforcement module for safety critical processing systems

Author(s): Francisco Bas
Published in: 2022
Publisher: Universitat Politecnica de Catalunya

Generación de un Módulo Optimizado de Inferencia en FPGAs con HLS

Author(s): Laura Medina
Published in: 2021
Publisher: Universitat Politècnica de València

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

Author(s): Tomas Picornell, Jose Flich, Duato Jose, Carles Hernandez
Published in: IEEE Access, Issue 8, 2020, Page(s) 194836-194849, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3033853

Achieving Diverse Redundancy for GPU Kernels

Author(s): Sergi Alcaide, Leonidas Kosmidis, Carles Hernández, Jaume Abella
Published in: IEEE Transactions on Emerging Topics in Computing, Issue vol. 10, no. 2, 2022, Page(s) 618-634, ISSN 2168-6750
Publisher: IEEE Computer Society
DOI: 10.1109/tetc.2021.3101922

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