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SELENE: Self-monitored Dependable platform for High-Performance Safety-Critical Systems

Deliverables

Initial software setup guide

Preliminary hypervisor and RTOS user manual (T3.1 - T3.5).

Use case descriptions and requirements

Description of the space, robotics and railway use cases, and their requirements on the SELENE platform (T1.3).

Dissemination & Exploitation report for PPR1, plans for PPR2

The initial dissemination plan reports on the dissemination activities undertaken in the first reporting period, and provides detailed plan for the rest of the project for both dissemination and exploitation including result from T5.4.

Website, flyer, initial dissemination and exploitation plan

Communication and dissemination materials targeting a variety of stakeholders, as well as the project website, and a plan for early dissemination and exploitation.

Preliminary SELENE System-on-chip description and configuration guide

First version of the FPGA board user manual (T2.1 - T2.6).

SELENE platform requirements and use constraints

Report collecting hardware and software SELENE platform requirements and use constraints (T1.1-T1.2).

FPGA platform definition

Specification of the characteristics needed by the SoC in the FPGA board to use, FPGA board choice, and fault mitigation measures needed for space environments (T1.4).

Preliminary software architecture Initial software enabling on target platform

Technical solutions description, and source code and configurations of hypervisor and Linux (T3.1 - T3.5).

Preliminary software architecture

Initial software solutions architecture and Hypervisor and Linux/RTOS setup (T3.1 - T3.5)..

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Publications

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems

Author(s): Carles Hernandez, Jose Flieh, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Ronnback, Johan Klockars, Nicholas McGuire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartet, Dierk Ludemann, Mikel Labayen
Published in: 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020, Page(s) 370-377, ISBN 978-1-7281-9535-3
Publisher: IEEE
DOI: 10.1109/dsd51259.2020.00066

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping

Author(s): Francisco Bas, Sergi Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo GIL, Oriol Sala, Fabio Mazzocchetti, David Trilla,Jaume Abella
Published in: 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Publisher: IEEE

On the reliability of hardware event monitors in MPSoCs for critical domains

Author(s): Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Enrico Mezzetti, Jaume Abella, Mikel Fernandez, Guillem Bernat, Francisco J. Cazorla
Published in: Proceedings of the 35th Annual ACM Symposium on Applied Computing, 2020, Page(s) 580-589, ISBN 9781450368667
Publisher: ACM
DOI: 10.1145/3341105.3373955

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem

Author(s): Vatistas Kostalampros, Jordi Ribes-González, Oriol Farràs, Miquel Moretó and Carles Hernandez
Published in: International Conference on Field-Programmable Logic and Applications (FPL), 2021
Publisher: IEEE

Empirical Analysis of the Specialization of a Diversity Metric per Circuit Path

Author(s): Sergi Alcaide, Carles Hernández, Jaume Abella
Published in: 17th Workshop on Silicon Errors in Logic - System Effects, 2021
Publisher: No oficial proceedings

Security, Reliability and Test Aspects of the RISC-V Ecosystem

Author(s): Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gurkaynak, Helena Handschuh, Carles Hernandez, Mike Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni
Published in: 2021 IEEE European Test Symposium (ETS), 2021, Page(s) 1-10, ISBN 978-1-6654-1849-2
Publisher: IEEE
DOI: 10.1109/ets50041.2021.9465449

Enabling hardware randomization across the cache hierarchy in Linux-Class processors

Author(s): Doblas, Max; Kostalabros, Ioannis-Vatistas; Moreto Planas, Miquel; Hernández Luz, Carles
Published in: 4th Workshop on Computer Architecture Research with RISC-V, 1, 2020
Publisher: No publisher

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation

Author(s): Oriol Sala, Sergi Alcaide, Jaume Abella, Guillem Cabo, Francisco Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Fabio Mazzocchetti
Published in: 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Publisher: IEEE

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

Author(s): Tomas Picornell, Jose Flich, Duato Jose, Carles Hernandez
Published in: IEEE Access, 8, 2020, Page(s) 194836-194849, ISSN 2169-3536
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI: 10.1109/access.2020.3033853