The increasing amount of data being processed in today’s electronic devices facilitating image and audio recog-nition, signal processing for smart sensors in medical devices, autonomous driving and machine learning re-quires new computing paradigms. In the conventional approach of computing the data is always sent forth and back between processor and memory. Moreover, in the recent approaches of making your device smart and intelligent, that data is even sent to the cloud for processing in big datacentres, and afterwards the results are sent back to your device. Obviously, that approach requires an always-on and high-bandwidth connection to the cloud, which is very energy hungry, time consuming and in-secure. Therefore, researchers all over the world aim at the realization of ultra-low-power edge devices that allow to process the data just in place where it is generated and by that to mitigate the need for big data transmission. In the year 2020 the BeFerroSynaptic pro-ject was formed among 11 partners from 5 European countries, funded by the European Commission. The sci-entists from industry and academia work together, combining their expertise in CMOS chip manufacturing and integration (XFAB, CEA), material and device development (NCSRD, IBM, HZB, NaMLab, TUD), simulation and modelling (UDINE,UNIMORE, ETH) as well as circuit design (UZH, UG).
Our approach is to expand the efficiency of conventional CMOS technologies by adding new functionalities of non-volatile ferroelectric memory devices into conventional CMOS logic technologies, that allow to store and to process the data locally where it is processed and by the adoption of neuro inspired architectures. Unlike the conventional vonNeumann architecture, that uses digital numbers for calculation, in our spiking neural networks the information is represented by event driven and correlated voltage spikes. In the BeFerroSynaptic project we focus on the development of two memory device concepts that utilize the ferroelectric polarization hysteresis to store the information - namely ferroelectric tunnelling junctions and ferroelectric field effect transistors. These tiny devices based on ferroelectric hafnium oxide are integrated on top of modern CMOS chips, directly into the metallization levels of the back-end-of-line process. The ultimate state of expansion of our approach is reached, where both logic and memory functionality of our ‘ferrosynaptic’ devices become synergized together in one synaptic unit.
