Periodic Reporting for period 2 - BeFerroSynaptic (BEOL technology platform based on ferroelectric synaptic devices for advanced neuromorphic processors)
Reporting period: 2021-07-01 to 2023-10-31
The increasing amount of data being processed in today’s electronic devices facilitating image and audio recog-nition, signal processing for smart sensors in medical devices, autonomous driving and machine learning re-quires new computing paradigms. In the conventional approach of computing the data is always sent forth and back between processor and memory. Moreover, in the recent approaches of making your device smart and intelligent, that data is even sent to the cloud for processing in big datacentres, and afterwards the results are sent back to your device. Obviously, that approach requires an always-on and high-bandwidth connection to the cloud, which is very energy hungry, time consuming and in-secure. Therefore, researchers all over the world aim at the realization of ultra-low-power edge devices that allow to process the data just in place where it is generated and by that to mitigate the need for big data transmission. In the year 2020 the BeFerroSynaptic pro-ject was formed among 11 partners from 5 European countries, funded by the European Commission. The sci-entists from industry and academia work together, combining their expertise in CMOS chip manufacturing and integration (XFAB, CEA), material and device development (NCSRD, IBM, HZB, NaMLab, TUD), simulation and modelling (UDINE,UNIMORE, ETH) as well as circuit design (UZH, UG).
Our approach is to expand the efficiency of conventional CMOS technologies by adding new functionalities of non-volatile ferroelectric memory devices into conventional CMOS logic technologies, that allow to store and to process the data locally where it is processed and by the adoption of neuro inspired architectures. Unlike the conventional vonNeumann architecture, that uses digital numbers for calculation, in our spiking neural networks the information is represented by event driven and correlated voltage spikes. In the BeFerroSynaptic project we focus on the development of two memory device concepts that utilize the ferroelectric polarization hysteresis to store the information - namely ferroelectric tunnelling junctions and ferroelectric field effect transistors. These tiny devices based on ferroelectric hafnium oxide are integrated on top of modern CMOS chips, directly into the metallization levels of the back-end-of-line process. The ultimate state of expansion of our approach is reached, where both logic and memory functionality of our ‘ferrosynaptic’ devices become synergized together in one synaptic unit.
Our approach is to expand the efficiency of conventional CMOS technologies by adding new functionalities of non-volatile ferroelectric memory devices into conventional CMOS logic technologies, that allow to store and to process the data locally where it is processed and by the adoption of neuro inspired architectures. Unlike the conventional vonNeumann architecture, that uses digital numbers for calculation, in our spiking neural networks the information is represented by event driven and correlated voltage spikes. In the BeFerroSynaptic project we focus on the development of two memory device concepts that utilize the ferroelectric polarization hysteresis to store the information - namely ferroelectric tunnelling junctions and ferroelectric field effect transistors. These tiny devices based on ferroelectric hafnium oxide are integrated on top of modern CMOS chips, directly into the metallization levels of the back-end-of-line process. The ultimate state of expansion of our approach is reached, where both logic and memory functionality of our ‘ferrosynaptic’ devices become synergized together in one synaptic unit.
Within the BeFerroSynaptic project the manufacturing processes for synaptic ferroelectric field-effect transistor (FeFET) and ferroelectric tunneling junction (FTJ) devices have been developed. Thereby, we improved the devices electrical characteristics by material stack and electrode engineering and solved the challenge to integrate the ferroelectric synaptic devices on CMOS wafers at BEOL-compatible temperatures as low as 400-450°C while keeping their required electrical performance characteristics to be used in our neuromorphic processor demonstrator.
The developments have been accompanied by detailed physical and electrical characterization. Major outcomes of our physical modeling approaches have been the understanding of the interplay between ferroelectric switching, depolarization fields, interface reactions and charge trapping phenomena. Different models such as a Python-based model describing charge transport and ferroelectric switching dynamics, a technology-computer-aided-design (TCAD) model for FeFETs and SPICE models for FTJ and FeFET devices have been implemented and are available for sharing with interested researchers.
At the end of the project a fully BEOL-integrated FTJ technology is available on wafer scale. This technology is based on CEA’s MAD200 vehicle in 130nm CMOS technology and was readily used for circuit design of our low-complexity demonstrator. The “2BeFerro”chip implements a Calcium-based learning rule by utilizing 64 Exp-I&F neurons with one learning synapse each.
Additionally, our “high-complexity” demonstrator TEXEL is a 9mm x 9mm neuromorphic chip that was designed using the XFAB 180nm XP018 technology. The chip features 180 adaptive-exponential integrate and fire (AdExp-I&F) neurons, each receiving input from 58 synapses. An overall number of more than 9000 ferroelectric 2 or 3 terminal synaptic devices can be integrated. CMOS wafers have been fabricated and are available for BEOL integration. Complete FeFET and FTJ devices have been integrated on top of CMOS samples on coupon level (wafer pieces). TEXEL chips have been packaged and functionality was verified. These chips are now available for utilization in different AI applications.
Besides our technical work, a significant effort was spent on dissemination of our results. PhD training courses have been held in three virtual sessions, reaching more than 50 attendees. Two workshops have been organized at international conferences, each reaching more than 60 attendees. Based on our results more than 60 peer-reviewed scientific papers have been published. Finally, different communication channels in social media and a web page were set up that aim at promoting the project, its activities such as workshops and trainings or the competences of our partners.
The developments have been accompanied by detailed physical and electrical characterization. Major outcomes of our physical modeling approaches have been the understanding of the interplay between ferroelectric switching, depolarization fields, interface reactions and charge trapping phenomena. Different models such as a Python-based model describing charge transport and ferroelectric switching dynamics, a technology-computer-aided-design (TCAD) model for FeFETs and SPICE models for FTJ and FeFET devices have been implemented and are available for sharing with interested researchers.
At the end of the project a fully BEOL-integrated FTJ technology is available on wafer scale. This technology is based on CEA’s MAD200 vehicle in 130nm CMOS technology and was readily used for circuit design of our low-complexity demonstrator. The “2BeFerro”chip implements a Calcium-based learning rule by utilizing 64 Exp-I&F neurons with one learning synapse each.
Additionally, our “high-complexity” demonstrator TEXEL is a 9mm x 9mm neuromorphic chip that was designed using the XFAB 180nm XP018 technology. The chip features 180 adaptive-exponential integrate and fire (AdExp-I&F) neurons, each receiving input from 58 synapses. An overall number of more than 9000 ferroelectric 2 or 3 terminal synaptic devices can be integrated. CMOS wafers have been fabricated and are available for BEOL integration. Complete FeFET and FTJ devices have been integrated on top of CMOS samples on coupon level (wafer pieces). TEXEL chips have been packaged and functionality was verified. These chips are now available for utilization in different AI applications.
Besides our technical work, a significant effort was spent on dissemination of our results. PhD training courses have been held in three virtual sessions, reaching more than 50 attendees. Two workshops have been organized at international conferences, each reaching more than 60 attendees. Based on our results more than 60 peer-reviewed scientific papers have been published. Finally, different communication channels in social media and a web page were set up that aim at promoting the project, its activities such as workshops and trainings or the competences of our partners.
AI systems can perform very complex tasks. The main AI applications can be segmented into technologies such as machine learning, language processing, speech recognition and image processing for the adoption in media, advertising, retail, telecom, IT, healthcare, automotive, transportation, agriculture, law or educational institutions. That is, the AI market is going to penetrate virtually all areas of our life. BeFerroSynaptic aims at providing an ultra-low power technology platform based on ferroelectric synaptic devices for advanced neuromorphic processors in AI applications.
Major progress beyond the state of the art was attained by designing for the first time FeFET based neurons as well as FeFET and FTJ based synaptic devices that are readily applied in a fully integrated technology platform.
The fully commercially available version of the BeFerroSynaptic technology platform could become available already in 2026 with target applications covering the full range of the AI market in both - cloud and edge computation. Thus, our results will have significant potential to boost the European industry’s strength in this segment. Moreover, BeFerroSynaptic targets at delivering a system which can be scaled up to the size of the Loihi and BrainChip NSoCs chips, but at a power consumption that is reduced by at least a factor of 10. This is made possible by the combination of novel low-power and non-volatile ferroelectric devices, sub-threshold circuits and the elimination of the von Neumann bottleneck. Thus, on the long term the BeFerroSynaptic technology platform has the potential to reduce the annual power consumption of information and communication technology by up to 100TWh, (assuming just an 1% impact on the power consumption in the related systems), and thus to make a significant contribution to the efforts towards a carbon neutral society.
Major progress beyond the state of the art was attained by designing for the first time FeFET based neurons as well as FeFET and FTJ based synaptic devices that are readily applied in a fully integrated technology platform.
The fully commercially available version of the BeFerroSynaptic technology platform could become available already in 2026 with target applications covering the full range of the AI market in both - cloud and edge computation. Thus, our results will have significant potential to boost the European industry’s strength in this segment. Moreover, BeFerroSynaptic targets at delivering a system which can be scaled up to the size of the Loihi and BrainChip NSoCs chips, but at a power consumption that is reduced by at least a factor of 10. This is made possible by the combination of novel low-power and non-volatile ferroelectric devices, sub-threshold circuits and the elimination of the von Neumann bottleneck. Thus, on the long term the BeFerroSynaptic technology platform has the potential to reduce the annual power consumption of information and communication technology by up to 100TWh, (assuming just an 1% impact on the power consumption in the related systems), and thus to make a significant contribution to the efforts towards a carbon neutral society.