Objectif
The high cost and slow turnaround times for customised ASICs currently prevent SMEs rom utilising full-custom ASICs, especially for small volumes. Moreover, the steadily increasing demand for mixed-signal ASICs requires that new design and process technologies be developed for fast turnaround, low-cost BiCMOS ASICs.
The project's aims are to:
- Drastically reduce the total cost per wafer of advanced BiCMOS ASICs (combination of 0.8 micron CMOS and 1.2 micron bipolar) with highly flexible combinations of breakdown voltages and frequencies. Costs will be cut more than 30% by developing and employing in pilot production. Objectives include an MeV-based ion implantation, low-thermal budget process flow which will save several process steps and eliminate the need for epitaxial silicon and diffusion steps; an advanced process flow allowing ASIC customisation in a few layers; and a novel ASIC wafer fab concept based on a new mini-environment clean room which will dramatically reduce the manufacturing equipment costs.
- Develop a dedicated and complete design environment that allows design houses and SMEs to smoothly transfer their designs to the 5-DAY ASIC fab, thereby providing a software environment fully supporting mixeD - mode designs, based on commercially available software packages, libraries of well-characterised cells and devices, and a complete design manual.
These developments will lead to the highly competitive capability of 5-day turnaround time for ASIC fabrication, as well as a lower threshold, especially for SMEs, to embark on ASIC design.
A new consortium incorporating all complementary skills of the supply chain has been formed to achieve the overall objective. The project is driven by an advanced ASIC manufacturer and includes partners with the following expertise:
- design-house for CMOS and bipolar ASIC
- MeV ion implantation specialist
- front-end equipment manufacturer
- manufacturing logistics expert
- ASIC end-users.
The starting point of the project is a newly built ASIC wafer fab based on an advanced mini-environment clean room with computer-controlled 6" single wafer processing, flexible enough to exploit the hardware, software, and process flow technologies to be developed by the consortium. Furthermore, a CAD design environment (on PCs as well as on workstations) together with a design manual including libraries covering all steps in the design flow will be created and optimised with respect to the 5-DAY ASIC facility.
End-users will validate the 5-DAY ASIC concept in the telecommunications and RF application sectors. The main deliverables will be the realisation of the 5-DAY ASIC wafer fab and two demonstrator 5-DAY ASICs manufactured with the developed design tools and process flow.
Champ scientifique
Thème(s)
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55129 MAINZ
Allemagne