Periodic Reporting for period 1 - 2D-HETERO (Synthesis and integration of wafer-scale van der Waals heterostructures for industrial nanoelectronic devices)
Reporting period: 2020-05-01 to 2022-04-30
Abundant-data computing such as big-data analytics, artificial intelligence (AI) and Internet of Things (IoT) demand extreme energy efficiency and concomitant improvement of cost performance of the electronic systems. Field-effect transistors (FETs) represent the fundamental building blocks for modern computer processors. The number of transistors in a typical microprocessor has followed a remarkable exponential growth since the 1960s, a trend known as Moore’s law. By making the device smaller, more transistors can be packed into a single chip with much improved performance and reduced cost. The continued miniaturization of silicon microelectronics has fuelled the exponential growth of the integrated circuits for over half a century. Today, as silicon transistors enter the sub-10-nm technology node with increasing technical challenges, the exploration of alternative device geometries or new channel materials is ever more important for future processor chip. Atomically thin two-dimensional (2D) semiconductors have attracted tremendous interest as a new channel material that could facilitate continued transistor scaling. To benefit from continuous scaling, the performance of the scaled 2D transistors needs to outperform Si technology nowadays. However, significant efforts are still required for channel material deposition, gate stack development, contact resistance reduction and CMOS integration, etc. The goal of 2D-HETERO project is to deposit high-quality and large wafer-scale 2D materials by CVD approach and integrate them in high-performance logic devices fabricated using industry-relevant tools and processes, and then enhance the device performance, yield and uniformity.
As planned, the project duration was 24 months and during this period, 2D-HETERO has been able to address most of the sub-objectives and achieve the set goals under corresponding work packages (WPs). In order to best align the goal of 2D-HETERO project with emerging R&D challenges and needs in the semiconductor industry and also the resources in Exploratory Logic Program at imec, the overall research plan carried out in the project was particularly adapted and focused on the following sub-objectives. The covered sub-objectives were grouped into 2 WPs as described below:
WP1: CVD growth of uniform, wafer-scale and high-quality 2D transition metal dichalcogenides (TMDs)
WP2: Fabrication and characterization of scalable 2D TMDs based FETs for high performance logic application
As planned, the project duration was 24 months and during this period, 2D-HETERO has been able to address most of the sub-objectives and achieve the set goals under corresponding work packages (WPs). In order to best align the goal of 2D-HETERO project with emerging R&D challenges and needs in the semiconductor industry and also the resources in Exploratory Logic Program at imec, the overall research plan carried out in the project was particularly adapted and focused on the following sub-objectives. The covered sub-objectives were grouped into 2 WPs as described below:
WP1: CVD growth of uniform, wafer-scale and high-quality 2D transition metal dichalcogenides (TMDs)
WP2: Fabrication and characterization of scalable 2D TMDs based FETs for high performance logic application
For WP1, two tasks were exploited. Task 1, CVD growth of uniform, and high-quality 2D materials on large scale wafers; Task 2, quality and thickness of the grown 2D materials. The achieved results are listed below:
We compared how two types of c-plane sapphire with distinct surface topography and structure impact the structural of a single layer of MoS2 deposited by MOCVD in a 200 mm industry-standard epitaxial reactor. The results show that by deliberately introducing a substantial off-axis cut angle of 1º to sapphire, the sapphire terrace width, step height -and thus also surface structure- become more uniform across the substrate, as opposed to on on-axis cut sapphire starting surfaces. The sapphire surface topography and structure can influence the nucleation of TMD deposited on top.
It is important to control the nucleation site and orientation of TMD growth to reduce the grain boundaries and even intra-grain defects in TMD monolayer. In this project, inspired by the learnings of TMD nucleation and orientation on single-crystalline sapphire, we proposed possible methods to control the seeding and orientation of the crystals during TMD nucleation on amorphous substrates.
Through controlling the nucleation site, orientation and lateral growth of TMD deposition on sapphire, we succeeded to increase the grain size of MoS2 monolayer from ≤1 µm to ≥50 µm.
We introduced an in-situ selective etching method to help smooth the surface of TMD layer, and thus ensure the uniformity of monolayer growth.
For WP2, two tasks were exploited. Task 1, Clean transfer of the grown 2D materials and fabrication of scalable 2D materials based MOSFETs; Task 2, characterization of the fabricated MOSFETs with 2D materials for high performance logic applications. The achieved results are listed below:
We further evaluated the impact of sapphire substrates on performance of the synthesized MoS2 MOSFETs. By transferring the MoS2 from both sapphire template types to Si target substrates, about ~2400 MoS2 field-effect transistors have been fabricated. The field-effect transistor performance results in a higher median electron mobility for MoS2 monolayers originating from off-axis cut 1º sapphire. Moreover, the device-to-device variability reduces both within and across wafers by at least a factor of ~2 in terms of the drain current at constant carrier density (Id_n), minimum subthreshold swing (SSmin), threshold voltage (Vt), the ratio of maximum and minimum drain current (Imax/Imin), and the field-effect mobility (µFE).
We for the first time statistically and quantitatively correlated monolayer MoS2 grain size with the performance of back-gate (BG) and dual-gate (DG) transistors. Large-grain MoS2 BG devices are more robust to channel surface clean, showing improved Imax and mobility after a soft H2-plasma clean, while the small-grain ones show degraded Imax and mobility after clean. We also find MoS2 channel with improved grain size requires additional engineering in high-k dielectrics deposition to ensure device performance gain. After fine tuning the high-k deposition process, we observe increasing the monolayer MoS2 grain size from ≤1 µm to ≥50 µm enhances field-effect mobility (~72%), transconductance (gm, ~75%) and reduces sub-threshold swing (SS, ~30%) for DG transistors.
We succeeded in precisely controlling the monolayer MoS2 thickness and uniformity through an in-situ selective etching method in WP1. In WP2, we statistically evaluated how this uniform monolayer TMD could help to enhance the FET performance at ultra-scale channel dimensions. Through statistically analyzing more than 15000 FETs, we report the demonstration of short channel transistors with IOFF≤10pA/µm for ultra-scaled devices, ION/IOFF>107, low median SSmin of 68mV/dec, and low VT variation with Pelgrom slope (AVT, a variability index) of 2.2mV-µm. This is similar to sub-10nm fin width (Wfin) Si FinFETs (EOT=0.8nm) with AVT=2.5mV-µm.
We compared how two types of c-plane sapphire with distinct surface topography and structure impact the structural of a single layer of MoS2 deposited by MOCVD in a 200 mm industry-standard epitaxial reactor. The results show that by deliberately introducing a substantial off-axis cut angle of 1º to sapphire, the sapphire terrace width, step height -and thus also surface structure- become more uniform across the substrate, as opposed to on on-axis cut sapphire starting surfaces. The sapphire surface topography and structure can influence the nucleation of TMD deposited on top.
It is important to control the nucleation site and orientation of TMD growth to reduce the grain boundaries and even intra-grain defects in TMD monolayer. In this project, inspired by the learnings of TMD nucleation and orientation on single-crystalline sapphire, we proposed possible methods to control the seeding and orientation of the crystals during TMD nucleation on amorphous substrates.
Through controlling the nucleation site, orientation and lateral growth of TMD deposition on sapphire, we succeeded to increase the grain size of MoS2 monolayer from ≤1 µm to ≥50 µm.
We introduced an in-situ selective etching method to help smooth the surface of TMD layer, and thus ensure the uniformity of monolayer growth.
For WP2, two tasks were exploited. Task 1, Clean transfer of the grown 2D materials and fabrication of scalable 2D materials based MOSFETs; Task 2, characterization of the fabricated MOSFETs with 2D materials for high performance logic applications. The achieved results are listed below:
We further evaluated the impact of sapphire substrates on performance of the synthesized MoS2 MOSFETs. By transferring the MoS2 from both sapphire template types to Si target substrates, about ~2400 MoS2 field-effect transistors have been fabricated. The field-effect transistor performance results in a higher median electron mobility for MoS2 monolayers originating from off-axis cut 1º sapphire. Moreover, the device-to-device variability reduces both within and across wafers by at least a factor of ~2 in terms of the drain current at constant carrier density (Id_n), minimum subthreshold swing (SSmin), threshold voltage (Vt), the ratio of maximum and minimum drain current (Imax/Imin), and the field-effect mobility (µFE).
We for the first time statistically and quantitatively correlated monolayer MoS2 grain size with the performance of back-gate (BG) and dual-gate (DG) transistors. Large-grain MoS2 BG devices are more robust to channel surface clean, showing improved Imax and mobility after a soft H2-plasma clean, while the small-grain ones show degraded Imax and mobility after clean. We also find MoS2 channel with improved grain size requires additional engineering in high-k dielectrics deposition to ensure device performance gain. After fine tuning the high-k deposition process, we observe increasing the monolayer MoS2 grain size from ≤1 µm to ≥50 µm enhances field-effect mobility (~72%), transconductance (gm, ~75%) and reduces sub-threshold swing (SS, ~30%) for DG transistors.
We succeeded in precisely controlling the monolayer MoS2 thickness and uniformity through an in-situ selective etching method in WP1. In WP2, we statistically evaluated how this uniform monolayer TMD could help to enhance the FET performance at ultra-scale channel dimensions. Through statistically analyzing more than 15000 FETs, we report the demonstration of short channel transistors with IOFF≤10pA/µm for ultra-scaled devices, ION/IOFF>107, low median SSmin of 68mV/dec, and low VT variation with Pelgrom slope (AVT, a variability index) of 2.2mV-µm. This is similar to sub-10nm fin width (Wfin) Si FinFETs (EOT=0.8nm) with AVT=2.5mV-µm.
Through the aforementioned work progress and innovation activities, there were two main findings/outcomes beyond the state of the art:
Reduce the variability of 2D material based devices from deposition through controlling the used template
Reduce the variability of 2D material based devices on par with the state-of-the-art Si FinFETs through precise monolayer growth control
Increased the grain size of 2D material and evaluate the impact of grain size/grain boundaries on dual-gate FETs integration and device performance
Reduce the variability of 2D material based devices from deposition through controlling the used template
Reduce the variability of 2D material based devices on par with the state-of-the-art Si FinFETs through precise monolayer growth control
Increased the grain size of 2D material and evaluate the impact of grain size/grain boundaries on dual-gate FETs integration and device performance