Periodic Reporting for period 1 - TECTONIC (Towards Employing Compilers for Thermal Management and Optimal Data Placement in Hybrid Cache)
Período documentado: 2021-01-01 hasta 2022-12-31
TECTONIC manages the on-chip temperature by leveraging application specific knowledge extracted at compile time in combination with new hardware mechanisms to distribute cache accesses to mitigate thermal imbalance and to reduce write endurance while maintaining high performance. Specifically, TECTONIC will meet the following objectives:
(1) To establish a relationship between data accesses and hot-spots at the CPU registers by investigating compute-intensive loops of contemporary large-scale applications (e.g. multi-media based applications, heavy algebraic computation etc.).
(2) To employ loop splitting towards ameliorating the write endurance problem in NVMs.
(3) To investigate the benefits of dynamic swapping of the contents of cache ways based upon write intensity.
(4) The knowledge deduced by the above investigations will enable us to analyse PowerPerformance-Thermal trade-offs and develop an optimal thermal-aware data placement strategy for NVM-based hybrid cache.
Additionally, the unavailability of proper architectural thermal simulators that can simulate the thermal behaviours of NVM-based hybrid caches keep this research area unexplored. Hence, the implementation of TECTONIC includes the creation of such a simulation framework, which will not only help us to accomplish the goals of TECTONIC, but will also kick off new research avenues.
These solutions are necessary towards generating efficient next generation comuting systems, which is a prime need for modern society. By providing such solutions, in broader scale, TECTONIC directly contributes towards mitigating the sustainable development goal, named, Industry, Innovation and Infrastructure of UN, which can be leveraged to mitigate some other SDGs of UN like, Quality Education, Sustainable Cities and Communities, etc.
(1) To establish a relationship between data accesses and hot-spots at the CPU registers by investigating compute-intensive loops of contemporary large-scale applications (e.g. multi-media based applications, heavy algebraic computation etc.).
(2) To employ loop splitting towards ameliorating the write endurance problem in NVMs.
(3) To investigate the benefits of dynamic swapping of the contents of cache ways based upon write intensity.
(4) The knowledge deduced by the above investigations will enable us to analyse PowerPerformance-Thermal trade-offs and develop an optimal thermal-aware data placement strategy for NVM-based hybrid cache.
Additionally, the unavailability of proper architectural thermal simulators that can simulate the thermal behaviours of NVM-based hybrid caches keep this research area unexplored. Hence, the implementation of TECTONIC includes the creation of such a simulation framework, which will not only help us to accomplish the goals of TECTONIC, but will also kick off new research avenues.
These solutions are necessary towards generating efficient next generation comuting systems, which is a prime need for modern society. By providing such solutions, in broader scale, TECTONIC directly contributes towards mitigating the sustainable development goal, named, Industry, Innovation and Infrastructure of UN, which can be leveraged to mitigate some other SDGs of UN like, Quality Education, Sustainable Cities and Communities, etc.
With the onset of the TECTONIC project, we started working on thermal properties of the registers built in state-of-the-art FinFET technology nodes. We investigated the thermal properties of FinFET based cores, caches, and registers and established relationships between data accesses and hotspots, by executing a set of benchmark applications in our simulation framework. and outcomes of this investigation are published in Computing Frontiers 2022 conference. We also started investigating non-volatile memory (NVM) based cache. We focused on the NVMs, like STT-RAM and ReRAM, for our investigation, due to their promising features over other NVMs. We started exploring the write related issues of the STT-RAM and realized the necessity of dynamic swapping of the cache blocks between the cache sets. Moreover, the relation between temperature, write endurance, retention time, device lifetime have also been investigated. The preliminary results are published in ASAP 2021 conference, whereas the detailed version of this work is still under review. Our comprehensive analysis includes a detailed design space exploration based on thermal analysis of the STT-RAM’s fundamental properties, along with the mitigation. We have also investigated the write issues in STT-RAM based multi-retention cache for heterogeneous systems. Preliminary results have been accepted for a publication in DAC 2023. A followup publication that will include a comprehensive thermal analysis of STT-RAM cache is in the final preparations. For ReRAM caches, we are currently working to develop a power-performance-thermal simulation framework which is already developed and is undergoing final verification for correctness. On completion of the verification process, the simulation framework will be released as an open-source tool for public use. We are developing a loop-splitting technique to overcome write limitations of NVM based caches, where write intensive data will be segregated at the compilation level, and will be placed in the appropriate retention zone by employing linker and cache controller together.
Publications:
1. Sukarn Agarwal, Shounak Chakraborty, Magnus Själander, “Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)”, DAC 2023. (accepted)
2. Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier, “DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.” IEEE TPDS, 2023.
3. Shounak Chakraborty, Vassos Soteriou, Magnus Själander, “STIFF: Thermally Safe Temperature Effect Inversion aware FinFET based Multi-core”, CF 2022.
4. Yanshul Sharma, Sanjay Moulik, Shounak Chakraborty, “RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore” DATE, 2022.
5. Yanshul Sharma, Shounak Chakraborty, Sanjay Moulik, “ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms” Journal of Supercomputing, 2022.
6. Sangeet Saha, Shounak Chakraborty, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier, “ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches” IEEE TCAD, 2022.
7. Sukarn Agarwal, Shounak Chakraborty, “ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache”, ASAP 2021.
8. Shounak Chakraborty, Magnus Själander, “WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption.” ACM TACO 2021.
9. Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier, “Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization” ACM TECS, 2021.
Publications:
1. Sukarn Agarwal, Shounak Chakraborty, Magnus Själander, “Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)”, DAC 2023. (accepted)
2. Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier, “DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.” IEEE TPDS, 2023.
3. Shounak Chakraborty, Vassos Soteriou, Magnus Själander, “STIFF: Thermally Safe Temperature Effect Inversion aware FinFET based Multi-core”, CF 2022.
4. Yanshul Sharma, Sanjay Moulik, Shounak Chakraborty, “RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore” DATE, 2022.
5. Yanshul Sharma, Shounak Chakraborty, Sanjay Moulik, “ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms” Journal of Supercomputing, 2022.
6. Sangeet Saha, Shounak Chakraborty, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier, “ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches” IEEE TCAD, 2022.
7. Sukarn Agarwal, Shounak Chakraborty, “ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache”, ASAP 2021.
8. Shounak Chakraborty, Magnus Själander, “WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption.” ACM TACO 2021.
9. Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier, “Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization” ACM TECS, 2021.
In TECTONIC, we are developing a thermal simulator for NVMs. To the best of our knowledge, no known simulator exists that can simulate the NVM's thermal properties, which we are about to address by deploying HotReRAM. We also developed techniques to determine on-chip thermal status for contemporary FinFET based multi-cores, another emerging research topic in the domain. As per state-of-the-art, exploration related to multi-retention NVMs considering their thermal property is unavailable. In TECTONIC, we also explored the write limitations of STT-RAM based caches, and a basic write-aware block migration technique was developed. Our simulation shows how this novel approach surpasses the state-of-the-art techniques. We also investigated the impact on fundamental properties of NVM based shared caches in state-of-the-art heterogeneous systems. We are currently developing a novel compiler based write intensive data segregation technique to mitigate write limitations of the multi-retention STT-RAM cache.
MSCA-IF certainly boosted the researcher’s career. At present Shounak is working as a Researcher at the same research group at the Department of Computer Science, NTNU, Norway, while focusing in the same research domain. The research experience gained during the fellowship has also helped him to get the Computer System Architect position at ZeroPoint Technologies AB, Gothenburg, Sweden.
The solutions developed and are being developed by TECTONIC are necessary towards generating efficient next generation comuting systems, which is a prime need for the modern society. By providing such solutions, in broader scale, TECTONIC directly contributes towards mitigating the sustainable development goal, named, Industry, Innovation and Infrastructure of UN, which can be leveraged to mitigate some other SDGs of UN like, Quality Education, Sustainable Cities and Communities, etc.
MSCA-IF certainly boosted the researcher’s career. At present Shounak is working as a Researcher at the same research group at the Department of Computer Science, NTNU, Norway, while focusing in the same research domain. The research experience gained during the fellowship has also helped him to get the Computer System Architect position at ZeroPoint Technologies AB, Gothenburg, Sweden.
The solutions developed and are being developed by TECTONIC are necessary towards generating efficient next generation comuting systems, which is a prime need for the modern society. By providing such solutions, in broader scale, TECTONIC directly contributes towards mitigating the sustainable development goal, named, Industry, Innovation and Infrastructure of UN, which can be leveraged to mitigate some other SDGs of UN like, Quality Education, Sustainable Cities and Communities, etc.