The project has already provided outstanding results towards its goal of demonstrating the ability of silicon technology to fabricate a large number of good quality qubits.
A linear 6-qubit system based on Si/SiGe have been operated by QuTech. In a 2-qubit system, the project has set up the state-of-the-art for two-qubit gates fidelity reaching 99.6%. This expected milestone was reached concomitantly with Australian and Japanese teams.
In addition, record Hahn-echo coherence time up to 88 μs for hole spin qubits have been measured by CEA-IRIG, it exceeds by an order of magnitude the best values reported so far for hole spin qubits
In parallel, the project has already laid solid technological foundations to massively fabricate Si spin qubits. The first step consists in transferring fabrication to industrial facilities to go from the scientific first to consistent and reproducible operation. For this statistical understanding is required to optimize technological parameters, to catch up with the other technologies, the consortium chose to develop three industrial fabrication technologies in parallel at Imec and CEA-Leti: Si/SiGe, Si/SiO2 on bulk devices and Si/SiO2 on SOI featuring at least two level of gates. IHP has developed versatile short loops fabrication flows to qualify materials and layouts.
Having these technologies has allowed for parallel evaluation and optimization of modules with a strong impact on performance: channel material, gate stack, comparison of electrical vs structural confinement, testing of different layouts and critical dimensions. The consortium in the next period will be able to measure, characterize and will help make decisions based on data to define the best technological fabrication process.
To quality the technology, there was a critical need for low temperature statistics. Within the consortium, we have established two kinds of statistical low T° platforms: first one relying on Bluefors 300mm cryoprobers (CEA-Leti one is in production and FhG is hooking its) or multiplexing boards (RF compatible has been developed by HEU).
In this first period, the project has built several tools to improve qubits quality, to provide automatic control and calibration and to help for assessment of the scalability.
On one hand, sophisticated superconducting amplifiers TWPA were developed (CNRS) to account from limitations from first generation of Josephson parametric amplifiers evidenced by HEU.
One the software side, a suite of simulation tools for qubits design relying both on home made and commercial softwares has been established (CEA-IRIG and Imec), collaborative calibration routines have been developed under FHZ responsibility. QM has developed QuEST, a simulator of universal quantum circuits, the objective is that the users will be able to input the desired topology and noise at the qubit level, creating a virtual silicon device that mimics the topology of the QLSI device for testing algorithms on it.
