Periodic Reporting for period 1 - eProcessor (European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem)
Période du rapport: 2021-04-01 au 2022-09-30
The eProcessor project is an ambitious combination of processor design based on the RISC-V open source hardware ISA, applications, and system software. The eProcessor project brings together multiple partners to leverage and extend pre-existing Intellectual Property (IP), combined with new IP that can be used as building blocks for future HPC systems, both for traditional and emerging application domains. As such, the eProcessor project’s overall goal is to create an open source full stack ecosystem (both software and hardware) by achieving the following objectives:
• The eProcessor technology is based on the RISC-V open source ISA, and it features high performance computing and data analytics accelerators coupled to a high performance, low energy out-of-order processor (Europe's first high performance out-of- order 64-bit RISC-V platform). This is a major first step in the direction of an open European software/hardware ecosystem, which will guarantee technology independence.
• eProcessor will meet the performance and energy requirements of new and existing HPC applications by co-designing solutions that provide high performance, low-power, and fault tolerance. Uniquely, we can specialize all components of the system in the context of a broad application domain: a combination of energy efficient accelerators, adaptive on-chip memory structures, and a flexible and high performance energy-efficient CPU, with the corresponding open source software stack.
• eProcessor uses a diverse set of applications in the HPC, artificial intelligence, deep learning, machine mearning, and bioinformatics domains to drive the design of the overall system. eProcessor is extending these applications and their frameworks to support the RISC-V ISA.
• Many applications use sparse data sets and/or low/mixed-precision. Instead of focusing on the peak performance of dense computations, eProcessor targets a broader collection of applications by developing a system targeting sustained application performance.
• The eProcessor partners are leveraging their existing IP from multiple European projects such as EPI, LEGaTO, MEEP, POP2 CoE, Tulipp, EuroEXA, ExaNeSt, and DeepHealth, extending their capabilities and improving their Technical Readiness Level (TRL). In addition, eProcessor is collaborating with two other projects of the EuroHPC program, SparCity and RED-SEA.
• eProcessor combines industry standard methodology and cutting-edge research to accelerate exploitation. Traditionally, academic hardware projects lack the rigor required in the industry. eProcessor extends traditional pedagogy into this new domain of high performance hardware design, and as a result, this project will deliver silicon-proven IP (higher TRL) that will provide a faster time-to-market and, as a result, higher potential for exploitation. The adoption of the IP from this proposal will be much higher than any other simulation- or emulation- only proposal because of the silicon-proven energy-efficient IP funded through this proposal.
• The eProcessor technology is based on the RISC-V open source ISA, and it features high performance computing and data analytics accelerators coupled to a high performance, low energy out-of-order processor (Europe's first high performance out-of- order 64-bit RISC-V platform). This is a major first step in the direction of an open European software/hardware ecosystem, which will guarantee technology independence.
• eProcessor will meet the performance and energy requirements of new and existing HPC applications by co-designing solutions that provide high performance, low-power, and fault tolerance. Uniquely, we can specialize all components of the system in the context of a broad application domain: a combination of energy efficient accelerators, adaptive on-chip memory structures, and a flexible and high performance energy-efficient CPU, with the corresponding open source software stack.
• eProcessor uses a diverse set of applications in the HPC, artificial intelligence, deep learning, machine mearning, and bioinformatics domains to drive the design of the overall system. eProcessor is extending these applications and their frameworks to support the RISC-V ISA.
• Many applications use sparse data sets and/or low/mixed-precision. Instead of focusing on the peak performance of dense computations, eProcessor targets a broader collection of applications by developing a system targeting sustained application performance.
• The eProcessor partners are leveraging their existing IP from multiple European projects such as EPI, LEGaTO, MEEP, POP2 CoE, Tulipp, EuroEXA, ExaNeSt, and DeepHealth, extending their capabilities and improving their Technical Readiness Level (TRL). In addition, eProcessor is collaborating with two other projects of the EuroHPC program, SparCity and RED-SEA.
• eProcessor combines industry standard methodology and cutting-edge research to accelerate exploitation. Traditionally, academic hardware projects lack the rigor required in the industry. eProcessor extends traditional pedagogy into this new domain of high performance hardware design, and as a result, this project will deliver silicon-proven IP (higher TRL) that will provide a faster time-to-market and, as a result, higher potential for exploitation. The adoption of the IP from this proposal will be much higher than any other simulation- or emulation- only proposal because of the silicon-proven energy-efficient IP funded through this proposal.
In the first reporting period, we achieved important results by completing the following work:
• Specification of the whole eProcessor system, including architecture, emulation, implementation environment, operating system, system software, compiler, performance tools, and application use cases.
• Design and implementation of a fully functional bare-metal out-of-order core with promising early results.
• Design and implement fully functional IP blocks for the NoC, the L2 caches, the AI accelerator based on systolic arrays, the mixed-precision functional units, the I/o devices and the peripherals.
• Design and implementation of a vector processing unit that executes SIMD instructions and has a direct path to memory.
• Development of a gem5-based simulation environment and a thorough performance evaluation of the eProcessor architecture with many different parameters.
• Development of a FPGA prototype of the eProcessor architecture that is able to successfully execute bare-metal workloads.
• Complete specification of the PCB, the pinout, and the package for the first eProcessor ASIC.
• Porting of an operating system tested on multiple RISC-V SDVs. The operating system is ready to be ported to the eProcessor ecosystem.
• Significant advances in porting and optimizing libraries for the eProcessor ecosystem, including efficient resource management techniques in OpenMP and software support for fault tolerance.
• Development of a LLVM compiler that is able to generate RISC-V SIMD code, including novel compiler support for low-precision floating poing operations.
• Porting of performance and debug tools to different RISC-V SDVs.
• Specification of the application use cases, porting to RISC-V, and clearly defining the plan for optimizing them on the eProcessor architecture.
• Development of a complete suite of microbenchmarks to evaluate the different components of the eProcessor architecture.
• Specification of the whole eProcessor system, including architecture, emulation, implementation environment, operating system, system software, compiler, performance tools, and application use cases.
• Design and implementation of a fully functional bare-metal out-of-order core with promising early results.
• Design and implement fully functional IP blocks for the NoC, the L2 caches, the AI accelerator based on systolic arrays, the mixed-precision functional units, the I/o devices and the peripherals.
• Design and implementation of a vector processing unit that executes SIMD instructions and has a direct path to memory.
• Development of a gem5-based simulation environment and a thorough performance evaluation of the eProcessor architecture with many different parameters.
• Development of a FPGA prototype of the eProcessor architecture that is able to successfully execute bare-metal workloads.
• Complete specification of the PCB, the pinout, and the package for the first eProcessor ASIC.
• Porting of an operating system tested on multiple RISC-V SDVs. The operating system is ready to be ported to the eProcessor ecosystem.
• Significant advances in porting and optimizing libraries for the eProcessor ecosystem, including efficient resource management techniques in OpenMP and software support for fault tolerance.
• Development of a LLVM compiler that is able to generate RISC-V SIMD code, including novel compiler support for low-precision floating poing operations.
• Porting of performance and debug tools to different RISC-V SDVs.
• Specification of the application use cases, porting to RISC-V, and clearly defining the plan for optimizing them on the eProcessor architecture.
• Development of a complete suite of microbenchmarks to evaluate the different components of the eProcessor architecture.
The eProcessor project expects to advance the state-of-the-art in different areas:
• Improve machine learning accelerators by developing arithmetic units to support a wide range of reduced and mixed precision and explore new formats for reduced precision floating-point training.
• Improve application performance using cooperative adaptive on-chip memories.
• Devise a coherent network on the chip to interconnect the CPU with the accelerators.
• Optimize and extend the OpenMP runtime and the compiler to leverage the resource management knobs of the eProcessor platform. This will allow OpenMP to guide cache coherence optimizations and to implement energy-efficient scheduling and synchronization.
• Design and integrate novel applications with hardware accelerators for artificial intelligence, machine learning, deep learning, and bioinformatics.
• Provide fault tolerance for critical processor structures with various error detection strengths (parity or lightweight ECC) and software support for efficient error recovery.
Beyond the advancements to the state-of-the-art, the eProcessor project has tremendous potential for innovation, particularly around the wide-spread adoption and rapid evolution of an ecosystem based on open hardware with the RISC-V ISA. RISC-V CPU technologies are forecast to exhibit a compound annual growth rate of 146.2% on average between 2018 and 2025, exceeding 62 billion deployed cores by 2025, over a range of market segments, including the computer, consumer, communication, transportation, and industrial markets.
In addition to this phenomenal growth rate, the eProcessor consortium recognizes viable opportunities for innovation as driven by two ongoing developments: (i) the convergence of computing platform requirements across HPC, artificial intelligence, machine learning, deep learning workloads, and bioinformatics; and (ii) the ever-growing demand for computational power by diverse application workflows. Power constraints necessitate a focus on efficiently using highly heterogeneous platform resources. To this end, the eProcessor project provides a roadmap for bringing key innovations toward developing an open source European full stack ecosystem based on a new RISC-V CPU coupled with multiple diverse accelerators.
• Improve machine learning accelerators by developing arithmetic units to support a wide range of reduced and mixed precision and explore new formats for reduced precision floating-point training.
• Improve application performance using cooperative adaptive on-chip memories.
• Devise a coherent network on the chip to interconnect the CPU with the accelerators.
• Optimize and extend the OpenMP runtime and the compiler to leverage the resource management knobs of the eProcessor platform. This will allow OpenMP to guide cache coherence optimizations and to implement energy-efficient scheduling and synchronization.
• Design and integrate novel applications with hardware accelerators for artificial intelligence, machine learning, deep learning, and bioinformatics.
• Provide fault tolerance for critical processor structures with various error detection strengths (parity or lightweight ECC) and software support for efficient error recovery.
Beyond the advancements to the state-of-the-art, the eProcessor project has tremendous potential for innovation, particularly around the wide-spread adoption and rapid evolution of an ecosystem based on open hardware with the RISC-V ISA. RISC-V CPU technologies are forecast to exhibit a compound annual growth rate of 146.2% on average between 2018 and 2025, exceeding 62 billion deployed cores by 2025, over a range of market segments, including the computer, consumer, communication, transportation, and industrial markets.
In addition to this phenomenal growth rate, the eProcessor consortium recognizes viable opportunities for innovation as driven by two ongoing developments: (i) the convergence of computing platform requirements across HPC, artificial intelligence, machine learning, deep learning workloads, and bioinformatics; and (ii) the ever-growing demand for computational power by diverse application workflows. Power constraints necessitate a focus on efficiently using highly heterogeneous platform resources. To this end, the eProcessor project provides a roadmap for bringing key innovations toward developing an open source European full stack ecosystem based on a new RISC-V CPU coupled with multiple diverse accelerators.