European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem

Informations projet

eProcessor

N° de convention de subvention: 956702

DOI 10.3030/956702

Date de signature de la CE 2 Decembre 2020

Date de début 1 Avril 2021

Date de fin 31 Mars 2025

Financé au titre de

• INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)

Coût total € 7 999 975,00

Contribution de l’UE € 3 999 987,51

Coordonné par

BARCELONA SUPERCOMPUTING CENTER CENTRO NACIONAL DE SUPERCOMPUTACION
Spain

Livrables

Documents, reports (4)

Project Management and Quality Guidelines
Dissemination and communication plan and Exploitation strategy
Simulation infrastructure and early architectural explorations
Dissemination and communication report

Demonstrators, pilots, prototypes (1)

FPGA emulation of single-core system

Open Research Data Pilot (1)

Data Management Plan (DMP)

Data Management Plan DMP

Other (2)

Release of the O/S, boot environment, compiler and performance tools for the FPGA-based single core system
Initial porting of the use case

Publications

Conference proceedings (4)

FastTrackNoC: A NoC with FastTrack Router Datapaths

Auteurs: A. Ejaz and I. Sourdis
Publié dans: IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022, 2022, Page(s) 971-985
Éditeur: IEEE
DOI: 10.1109/hpca53966.2022.00075

Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs

Auteurs: Miquel Moreto Santiago Marco-Sola
Publié dans: 4th HPC Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), 2022, Page(s) 1
Éditeur: IEEE

FPGA checkpointing for scientific computing

Auteurs: Perelló Bacardit, Marc; Bautista Gomez, Leonardo; Unsal, Osman Sabri
Publié dans: IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, ISBN 978-1-6654-3370-9
Éditeur: IEEE
DOI: 10.1109/iolts52814.2021.9486693

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Auteurs: Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, and Miquel Pericas
Publié dans: IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2022), 2022
Éditeur: IEEE

Peer reviewed articles (1)

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Auteurs: Jing Chen; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs
Publié dans: Transactions on Architecture and Code Optimization (1544-3566) vol.19(2022), Numéro 15443566, 2022, ISSN 1544-3566
Éditeur: Association for Computing Machinary, Inc.
DOI: 10.48550/arxiv.2201.12186