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In-situ technique for innovative reliability assessment of advanced, high density electrical interconnection


Impact on predictive capability:
-The in-situ technique is by far more effective than the conventional to point out the specific failure mode induced by the stress. This was clearly demonstrated in the case of the leakage tests done on underfilled flip chip assemblies: conventional off-line measurement apparently did not show failures, whereas the in-situ technique recorded erratic spikes of the current leakage outside the target limits;
-The behavior expected at the beginning of the project, i.e. a drift according to a continuous curves relative to only 1 aging mechanism, following the law "the higher the drift, the shorter the time to failure" has been checked only for one test structure (Ag- filled polymer via in thermal cycle test);
-The in-situ method gives an accurate monitoring of the resistance of connections during aging. In this way, it gives better information on the aging than the conventional tests. Example: the in-situ test method gives in hot storage an image of the materials evolution for soldered interconnections (CSP/BGA).

Impact on throughput time:
-The higher measuring resolution allows to select more stringent failure criteria compared to conventional testing. For flip chip assemblies in T-shock test, it was shown that by bringing down the failure criterion from 1W to a drift of 50%, the throughput time can be reduced with a factor 2 to 6;
-For embedded resistors in the IMEC 1 technology, change of performance could be shown accurately by the insitu technique. Thus, under well known stresses, it is possible to determine the resistor drift. That is to say, the moment when the device is going out of specifications;
-For adhesive interconnections we clearly see a post-cure effect during the insitu tests at high stress levels. This means that during accelerated tests at high stress levels, we measure the intrinsic robustness of the interconnections and not the actual quality. If stress in the field does not induce the post-cure effect, life testing should be done at lower stress levels, closer to the field conditions. This is only posible with insitu testing with high measuring resolution;
- Statistical relevance;
-Prototypes of test systems have been made available allowing 256 channels to be tested in one run. This allows proper statistical analysis of the results.

Applicable to high density interconnections:
-The test structures selected in this project clearly demonstrate that the insitu approach is very well suited for advanced, high density interconnections;
-Generally speaking, the in-situ tool becomes very interesting when the aging mechanisms /failure modes are clearly known and understood. Thus, this opens the way to short and efficient testing. Compared to conventional accelerated testing, it gives more accurate and more reliable measurements because it prevents from any disturbance due to external factors and ensures that the testing conditions will not change;
-Potential application areas of the in-situ technique are:
-Automation of accelerated testing;
-Determination of aging mechanisms for new technologies;
-Comparison of new batches of materials in a short test;
-The ITERELCO project revealed also some limitations of the approach. Suggestions for improvement and a guideline how to use in-situ technique were formulated.
Portable products and products for harsh environments are the booming markets for the electronic equipment sector. As a consequence, the electronics industry is confronted with ever increasing functionality and integration on single chips, reducing size, greater power, reduced weight and higher temperature applications. Therefore, new advanced electrical input/output (I/O) interconnection technologies and materials at the packaging level are continuously being developed and have to be proved. One of the majorchallenges in the development of new advanced electrical I/O interconnect technologies at the packaging level, is to evaluate, optimise and qualify their reliability. The reliability of electrical I/O's is one of the major concerns of the electronic packaging industry. A major difficulty encountered today is that for new interconnection techniques, the aging kinetics are not known and that the reliability qualification time using conventional techniques is too long, with a negative influence on the time to market of the product.

In the ITERELCO project, new reliability evaluation techniques for electrical I/O interconnects will be developed and validated. These new techniques should meet the following demands: a) short testing time (in the order of 100hours) b) high sensitivity to the major ageing mechanisms of electrical I/O'sc) high predictive capability for real life performance In the validation phase of the project, the correlation between conventional test results and results obtained with the new techniques will be studied. Therefore, the reliability of a number of selected advanced interconnect technologies (e.g. flip chip with an isotropic and isotropic adhesives and polymer stud grid arrays) will be fully evaluated, both with conventional and innovative techniques. For this purpose, a Consortium has been formed, consisting of three end-users in the packaging industry in complementary application fields, a reliability test system manufacturer to provide prototypes, and two research centres specialised in the field of reliability in electronic packaging. Only Consortia like this can eventually ascertain the competitiveness of the European industry in the exploding markets of portable products and products for harsh environment. BE97-4914

Funding Scheme

CSC - Cost-sharing contracts


Nederlandse Philips Bedrijven BV
5600 MD Eindhoven

Participants (5)

Celestica Italia s.r.l.
Via Lecco
2059 Vimercate
Destin N.V.
3590 Diepenbeek
75,Kapeldreef 75
3001 Heverlee
1,Wetenschapspark 1, Universitaire Campus
3590 Diepenbeek
Siemens Automotive SA
Avenue Du Mirail
31036 Toulouse