Testing hi-resolution and hi-temperature I/O interconnects
Electronic packaging is driving the boundaries of single chip technology, and as such they are constantly being reduced in size, have greater power and have to perform within adverse temperature parameters. As a result of the future demands on electronic packaging including temperature deviation environments, the chips used, employ a new breed of Input/Output interconnection technologies and materials. The main aim behind the project was to develop and validate new reliability evaluation techniques for electrical I/O interconnects. Such techniques had to be able to meet the demands of short testing time, high sensitivity to aging I/O electrical mechanisms and high predictive capabilities. Testing concentrated on the comparative results between conventional and advanced interconnect technologies, focusing on flip chips, with isotropic adhesives and polymer stud arrays. There were three major obstacles to overcome for the packaging industry, which were chip evaluation, optimisation and reliability. With the reliability obstacle, use of conventional techniques did not yield sufficient information on aging kinetics and the reliability qualification time was too long. Thus it became necessary to develop new evaluation techniques for electrical I/O interconnects. Due to limitations in the temperature cycling process, the Devices Under Test (DUT) had to be processed using the Local Temperature Sensing (LTS) concept. This enabled the socket in the DUT to be measured continuously whilst it was still in the cycling chamber. Then with the use of a correction algorithm to set the local temperature deviation, the contact value resistance was able to measure the actual temperature at specific points in time. Additional developments bore fruit when the LTS concept was used in an air-to-air thermal cycling system, whereas previously it had been restricted to batch type furnaces. The Dutch company behind these advances have also overcome the avoidance of unwanted leakage currents due to water condensation when switching from the high to low temperature chambers. A prototype/demonstrator is available for testing and the patents have been applied for, but not yet granted.
