Communication between processors is a fundamental problem in parallel and distributed architectures, since it is often the major bottleneck lowering the performances of the systems.
In this setting the planned research focuses mainly on deadlock-free routing schemes, compact routing and efficient broadcast and gossiping operations. In every case we want to determine optimal and efficient results for the most commonly used interconnection networks both in terms of time required to perform communications and space (memory) necessary at each processor to store the required information.
The planned research activity is relevant to industry since the interval routing scheme (one of the routing schemes which will be further investigated) has been recently implemented in the INMOS Transputer Router chips. Moreover the host institute currently maintains contacts with many computer manufacturer companies, such as DEC and SIMULOG.
The applicant comes from a less favored region of the Community (Abruzzi - Italy).