Exploitable results AVHDL development environment for reusable VHDL descriptions Virtual hardware description language (VHDL)-integrated common environment (ICE) is a VHDL development environment for design teams working on multiple versions of reusable VHDL descriptions. Built for heterogeneous computing environments, VHDL-ICE helps VHDL development teams build virtual components in a reliable, reproducible way. It also allows VHDL developers to address previously intractable problems in the management of intellectual property rights. VHDL-ICE's advanced capabilities directly address previously intractable problems in the management of Intellectual Property Rights (IPR) for VHDL development teams. Current VHDL-based design methodologies include developing and maintaining multiple virtual components( VC) concurrently, guaranteeing the accuracy of product releases, re-building previously-shipped or acquired VHDL VCs enforcing uniform development policies, and handling requests for technology releases. By solving these problems, VHDL-ICE helps VHDL development teams build all of their VCs reliably, in a reproducible way, without error. The first stage of VHDL-ICE provides facilities for teamwork, organization and workspace management, including management, navigation and assessment facilities for VHDL VCs, without forcing VHDL developers to change their development tools or the way they work. The second stage of VHDL-ICE includes version control and configuration management. Eventually, VHDL-ICE will be enhanced to support design methodology management and process control. A VHDL design studio Virtual hardware description language (VHDL) Design Studio (VDS) is a generic graphical user interface developed for any computer aided design (CAD) tools based on the LEDA VHDL Verilog System (LV2S). LV2S is a front-end compilation environment developed by for VHDL and Verilog-based applications. This front-end system allows the syntactic and semantic check of IEEE-1076 VHDL and IEEE-1364 Verilog description and their storage in a binary data format. LV2S is aimed at CAD tool developers. VDS offers a user-friendly interface for the management of VHDL source code files and associated VHDL libraries in the LV2S environment. Menus allow the definition of VHDL projects composed of sets of source files that must be compiled into VHDL libraries. Compilation processes may be performed on a file by file basis, or for a full library, or for the full project. From the compiler message window, a mouse click gives instant access to the corresponding VHDL source code allowing fast turnover during the VHDL development process. A library window displays the content of each VHDL library, on a per unit basis, and allows menu driven action on the VHDL libraries or units. Being a generic graphical user interface, VDS is an open system allowing the integration of LV2S-based applications. Facilities are provided for controlling the execution of such applications, including the display of results by the way of icons of specific result windows. TIMING AND STRUCTURAL INSPECTION QUALITY TOOL : AUDIT The result is a software tool suited for the structural analysis of Very Large Scale Integration (VLSI)circuits or blocks. The tool basically operates at the netlist level and is capable of identifying connection problems such as: asynchronous paths unconnected signals clocking problems clock synchronization testing devices control, etc. The main characteristics of AUDIT are: It offers the user a very useful and complete analysis environment for VLSI circuits. It incorporates design libraries for several manufacturers. Furthermore, in provision of the continuous changes and updates of these libraries, as well as of the high probability of manufacturing circuits with new providers, a procedure to support new libraries has been designed with the objective of avoiding very expensive engineering costs and tool support. AUDIT has been designed to be easy to use. It has a self-explanatory user interface, that permits the user to handle the tool in an intuitive manner. On the other hand, AUDIT incorporates an exhaustive control of tool manipulation errors, showing an error window in the screen explaining the possible cause of the error. AUDIT incorporates a continuous information system, that shows the user detailed information about the option of the tool that is being executed. By using the tool, the user can identify without long simulations, a wide variety of structural potential problems in a circuit netlist that could cause a bad behaviour, a not testable circuit block or a timing problem. The quality of a synthesis process can be perfectly assessed with the AUDIT tool as well. The tool runs on SUN Workstation platforms using SUNOS or Solaris. The market for this tool is predominantly with digital IC design groups. The tool is now under test in a couple of beta sites: ES2 Rousset and the DIE group of the Polytechnic University of Madrid. VHDL Quality Tool Kit (VHDL QTK) The VHDL Quality Tool Kit (VHDL QTK) is a set of tools for checking the quality of synthesisable VHDL descriptions for the purposes of reusability and reliability. The current version of the tool includes checkers to perform: - Sensitivity List Analysis: Reporting potential problems in the sensitivity list of processes. - Architectural Description Style Analysis: Classifies architectures regarding their description style (behavioural, data-flow, structural, mixed). - Object Usage: The Object Usage Analysis searches thoroughly in design units for unused objects, reporting declared and not used ports, signals, variables and constants or generics. - Hard Coded Integer Values Analysis: Integers hard coded in the VHDL descriptions are detected and highlighted. - Tri-State Signals Analysis: This analysis will highlight those signals that are going to be synthesised as tri-state buffers. - Clock and Reset Analysis: For every clock described in the design this analysis points out: - Whether the clock is driven from combinational or sequential logic, or from an external port. - Signals and variables triggered by the clock signal. - Whether the clock drives combinational logic, data of flip-flops, etc. - Dependencies with other clocks. For every reset described in the design this analysis points out: - Whether the reset comes from combinational or sequential logic, or from an external port. - Signals and variables initialised by the reset signal - Whether the reset is source of combinational logic, data of flip-flops, etc. - Dynamic or static initialisation. The GUI shows the results of the checkers in a compact tabular form with hypertext. This allows design managers to quickly evaluate the quality of a VHDL description or library. The information, warnings or source of problems provided by the checkers is directly highlighted on the VHDL source code. Searching for OpenAIRE data... There was an error trying to search data from OpenAIRE No results available
