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Exploitable results
The central issue of Optically Interconnected Integrated Circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced Very Large Scale Integration (VLSI) Complementary Metal Oxide Semiconductor (CMOS) designs. The envisaged route to solving this problem offers high-throughput data interconnects on chip and Multi-Chip Module (MCM) level, facilitating implementation of new digital architectures and systems.
OIIC will find solutions to the difficulties of handling high-throughput data transfer by electronic interconnects to, within and between silicon VLSI chips, arising from the ever-increasing IC complexity, speed and interconnection requirements. Several European research projects (e.g. OLIVES, HOLICS and SPIBOC) have proposed optical solutions to this interconnect bottleneck at a higher level of interconnect hierarchy. It is the main goal of this project to establish key technologies and define relevant processing architectures allowing introduction of area (as opposed to edge) optical interconnections for intra- and inter-MCM data exchange. The data rate per channel will be compatible with extrapolated CMOS clock rates and the number of interconnects will be in the 100 to 1000 range, leading to aggregate bit rates in the order of 100 to 1000 Gb/s . This interconnect capability will alleviate the interconnection problems imposed by pure chip-edge electrical interconnects, enhancing processing power beyond performances offered by purely electrically interconnected VLSI chips. The project will demonstrate the advantages of high-throughput optical chip-to-chip interconnects by integrating area optical interconnections with standard CMOS chips, also addressing cost-effectiveness as well as manufacturability. Processor architectures, where the area optical interconnects offer substantial benefits, will be identified.
Based on the new technologies, two link demonstrators will be constructed, a highly parallel link running at moderate bit rates called Photonlink and a 2x8 high-speed link, called Gigalink.
In addition to the link demonstrators, a system demonstrator will be implemented. This demonstrator will be connecting two packaged, programmable chips, through area optical interconnect (maximum 4 8x8 unidirectional links per chip). These chips will harbour a programmable FPGA-architecture. Aggregate bit rate (I/O per chip) will exceed 10 Gb/s.
Project URL : http://www.intec.rug.ac.be/OIIC
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