Objective
In this project, we want to find solutions to the difficulties of electronic interconnects to handle high throughput data transfer within and between silicon VLSI chips. This fundamental problem arises from the ever increasing IC complexity, speed and interconnection requirements. Several European research projects (e.g. OLIVES, HOLICS and SPIBOC) have proposed optical solutions to this interconnect bottleneck at a higher level of interconnect hierarchy (inter-cabinet and back plane interconnects). It is the main goal of this project to establish key technologies and define relevant processing architectures allowing introduction of area (as opposed to edge) optical interconnections for intra- and inter-MCM data exchange.
The data rate per channel will be compatible with extrapolated CMOS clock rates (0.5 to 1.5 GHz) and the number of interconnects will be in the 100 to 1000 range, leading to aggregate bit rates in to order of 100 to 1000 Gb/s. This will alleviate the interconnection problems imposed by purely chip edge electrical interconnects, enhancing processing power beyond performances offered by purely electrically interconnected VLSI chips.
The project will demonstrate the advantages of high-throughput optical chip-to-chip interconnects by integrating area optical interconnections with standard (i.e. foundry based) CMOS chips, also addressing cost effectiveness as well as manufacturability. Processor architectures where the area optical interconnects offer substantial benefits will be identified. A CMOS VLSI chip will be designed, implementing at least partly such an architecture, and equipped with integrated analogue driver and receiver circuitry to interface the digital processing module to the optoelectronic components. Source arrays (VCSEL and LED arrays) and detector arrays will be developed in the project, as well as the micro-optical hardware assuring the intra-MCM or inter-MCM link. Because of the requirement for an area interconnect, these optoelectronic components will be directly mounted on the silicon CMOS chip. This micro-optical hardware will consist of novel Optical Pathway Blocks (OPBs), based on polymer technology.
In the proposed generic interconnect concept, a direct optical interconnect to any location on a chip is provided. Depending on the distance of interconnect (intra-chip, intra-MCM or inter-MCM), a different type of polymer Optical Pathway Block is used (rigid or with flexible waveguide arrays with or without connectors).
In order to assess the performance and demonstrate the advantages of processing systems using these area optical interconnects, a demonstrator will be built towards the end of the fourth project year, which implements the inter-MCM connectorised interconnect in a functionally operating processing system.
Prior to this final demonstrator, technology demonstrators will be assembled (towards the end of the second project year). These demonstrations will allow to assess available component, hybridisation and packaging options, providing necessary information for the final demonstrator design.
Fields of science (EuroSciVoc)
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CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques.
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Topic(s)
Call for proposal
Data not availableFunding Scheme
EIF - Marie Curie actions-Intra-European FellowshipsCoordinator
3001 Leuven
Belgium