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Advanced techniques for high temperature system-on-chip


To demonstrate the capabilities of the HTST system several SoI memories, which would eventually be incorporated into an automotive application, were tested. The capability of the system to perform as an “intelligent burn-in” system were satisfactorily demonstrated, the test results for a range of temperatures were acquired and subsequently displayed as a series of bitmaps whose contents altered as the temperature changed. In a further demonstration of the system’s capabilities the “digital” core, which would be part of the demonstration vehicle for the project as a whole, was also tested using scan path methodology; the scan chain control signals were activated by the test system, which also acquired the test results. Some basic tests were also performed on a commercially available ADC, demonstrating that the system can be applied not only to memory and digital circuits but also to analogue circuits.
A verification program capable of handling very complex and large circuits has to be used for the verification of the ATHIS ASIC. DRACULA (R) is such a program. To make it usable for the consortium, a run-set that is a set of rules for the XI10 SOI technology process able by DRACULA was written. It includes a check for design rule errors, electric rules and antenna rules, parasitic extraction and a layout versus schematic check. After thoroughly reliability tests the run-set was completed and is available in the form of software code. It is included in the X-FAB design kit XI10 and is therefore usable outside the consortium as well.
Semiconductor power devices are typically rated for operation below 150C. While digital and low power devices have been characterized at elevated temperatures, little data are available for power semiconductors over 175C. In most cases, the device is derated to zero operating power at 150-175C. We have investigated the state of the art of the high temperature commercial devices. In this sense, we found many low voltage, low on resistance MOSFET devices with an operating temperature up to 175C. Moreover, we found another reference, the IR1704 from International Rectified, which is an HEXFET Power MOSFET that was initially expected to operate at temperatures up to 200C. However, this component has been withdrawn of the market due to unknown reasons. Consequently, we have exhaustively studied the basic cell of a MOSFET by means of numerical simulations in order to optimise the device for an operating temperature up to 200C. This work has been focused in different ways: the identification of hot spots for different basic cell geometries, the analysis of the leakage currents with temperature, the optimisation of the device for logic level operation and finally the dynamic behaviour analysis by means of transient simulations. Based on the simulations results, we have chosen an optimum cell pitch distance that shows the minimum peak temperature in the JFET region. Since the increase of the leakage currents is the main constrain at high temperature operation, we have also reduced the body-epitaxy junction area, since this junction is mainly responsible for the leakage current generation. As regards the logic level operation required for the demonstrator, we have used a high dose implantation in the channel region in order to adjust the threshold voltage (around 1V) without degrading the ON-resistance values and maintaining a thick gate oxide layer to increase the reliability in the gate region. The optimisation of the basic cell together with the optimization of the back-end processes (thick metallization, gold metal...) and package (solder alloy, substrate, coatings) allow the operation of the power device at 200C external temperature. We have packaged different large area devices from different wafers on DCB (Direct Copper Bonded) substrates. Specific on-resistance, threshold voltage and leakage current have been measured on package devices at 200C external temperature: the on-resistance values are in the range of 35 m¥Ø at gate voltage of 5V, the threshold voltage is 1.3V and the leakage current at 80% of the breakdown voltage is 1.2mA.
Due to a larger band gap than Si, SiC is considered as a candidate semiconductor for high temperature operation devices fabrication. SiC power devices are also of great interest due to the superior electrical and thermal characteristics of this semiconductor. Consequently, we have studied the most technologically advanced SiC power devices, the Schottky diode for high temperature operation. For this purpose, we have modified a SiC Schottky diode process previously developed for standard applications to produce high temperature SiC Schottky diodes. In this sense, we have basically changed the Schottky metal, using Ni instead of Ti for its higher Schottky barrier height. 600V-2A diodes have been fabricated and packaged. Back end process (thick metallisation and thick organic passivation) and package (solder alloy, substrate, coatings...) materials have been chosen to allow operation at 200C external temperature. The devices have been electrically characterised up to 200C. In the reverse mode at 200C, the leakage current of the SiC diodes is 3 orders of magnitude lower than Si Schottky devices. Switching times are low and almost temperature independent and the SiC diodes result faster than Si bipolar diodes on the whole temperature range. Operation temperature is limited by the back end process and packaging materials.
A new family of ultra-low power (ULP) circuits has been developed and patented based on multi-threshold voltage MOSFETs and the reverse ULP diode concept. These have now been fully experimentally verified on UCL fully depleted SOI CMOS process up to elevated temperatures. The basic advantage of the ULP circuit family is to achieve a much lower static power dissipation than standard MOS circuits, by biasing the n-MOS (resp. p-MOS) transistors in static operation (i.e. stand-by) at a gate-to-source voltage lower (resp. higher) than zero and hence a much lower leakage current. Indeed, when compared to the classical MOS diode, the new ULP diode features a much lower reverse leakage current. Based on the ULP diode, - The ULP memory cell has been proven to yield reduced static consumption, and better high temperature behaviour than standard six-transistor SRAM. The ULP memory functionality has been tested up to 280°C. - A voltage doubler based on Dickson’s charge pump architecture has been designed either with a standard MOS or ULP diodes. Under high temperature conditions, the ULP charge-pump operates much better, demonstrates a much resistance to low clock frequencies and a much better efficiency than the standard MOS circuit. Furthermore, the concept has been extended to data node keepers in MTCMOS low-power digital circuits. In circuits with idle or stand-by modes which disconnect unused parts of the logic for minimizing static power consumption, a drawback is the loss of the information stored on internal floating nodes. This requires the introduction of additional keepers or special flip-flops. Our ULP solution minimizes their inconvenience with regards to associated timing and area overheads.
A High Temperature driver for Power MOSFET. This circuit is the analog part of a Power MOSFET driver. Its function is to drive the gate of a power MOSFET. It will work at temperature up to 225°C. As part of a more complete system, exploitation outside of this project would require additional work. This circuit could be used in several custom applications to control motor or power converter for example. This circuit can be used by any system design companies that want to develop a high temperature system. Targeted market are Automotive and Aerospace, to improve engine efficiency and security and decrease weight. Well logging companies are also willing to use this kind of circuit to improve well efficiency or in the case of geothermal application, to access deeper hot water sources. This will improve both fossil and renewable energy use.
Part of the overall project is to be able to test a range of macro blocks (sub-circuits) realised in SoI technology at temperatures around 250-300C. It is also necessary to perform, as far as possible, accelerated life testing on these circuits. This will require stimulating the circuits for approximately 1000 hours at elevated temperatures and voltage, the acquisition, logging and subsequent processing of test data. It would not only be extremely costly but also impractical to try to interface a commercial logic/memory tester to the oven and run the system continuously for 1000hours. Consequently a scheme is being developed which embodies the Built Off -Chip Self Test (BOST) Voltage/Current test strategies to be used over a test source oven interface. The test source/oven interface comprises a mix of software and hardware. The software aspects of the interface have been implemented in LabVIEW, which is a graphical programming language developed by National Instruments. “Virtual Instruments” (VIs) are created, which are customised programmable functions used to realise a range of instrumentation functions rather than employing dedicated hardware. This approach has the major advantage of flexibility and can accommodate changes in requirements with relative ease. The modular structure of the scheme being developed permits the resulting system to be used as: - A pattern generator creates the test stimuli for the circuit under test. - A logic analyser compares actual and expected responses from the circuit under test. - A combination of pattern generator and logic analyser emulates BOST. - A data acquisition system storing and manipulating test results. The hardware aspects of the interface comprise several PCBs (mother board and 3 daughter boards) and the “off-chip” current monitor. Success Factors: - Understanding of test methodologies will ultimately enhance reliability. - Cost reduction in manufacture. - Cost reduction in digital ATE and reliability test equipment End Users: - Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc. - Manufacturers of semiconductors for HT applications.
The development of the initial HTST (High Temperature Stress Test) System was an integration of two previous tasks, namely, 'Tester /Oven Interface Development' and 'Implementation of BOST for V/I Testing'. This merger resulted in the creation of an 'Intelligent Burn-in' system in which devices can be continuously stimulated by functional test patterns and their responses continuously monitored whilst being subjected to high temperature stress over a prolonged time period. The current system which, has commercial, potential, is called LOCHITT (LOw Cost HIgh Temperature Stress Test) features: Test software also includes Analogue Waveform Editor (AWE), Digital Waveform Editor(DWE). The DWE and AWE can be used easily to design the test patterns providing greater flexibility for the user to modify/generate waveforms in order to test different types of analogue and digital functions. Overall the test system has the capability of performing: - “Current Ratio” Measurements. - Memory Tests. - Scan Testing. - Dynamic “Burn-in”. - Analysis of high temperature test runs. - Basic Tests on ADCs/DACs. It is considered that this system has commercial potential, finding wide spread use in application where it is necessary to establish the reliability of semiconductor systems without tying up expensive ATE for long periods of time, which would not only be costly but also impractical. Applicable to a wide range of test scenarios, e.g. reliability testing, failure mode analysis etc. System is highly flexible and low cost. Would be of interest to companies involved with the manufacture or use of high temperature electronic devices and systems. This spans companies from the automotive industry, oil well exploration, aeronautics/aerospace etc.
It has been recognised for sometime that the standard logic test methods based on “stuck-at” fault testing have had serious limitations in detecting process oriented faults which increase the “off-state” current in a circuit but do not manifest themselves as “stuck-at” faults; these types of faults ultimately affect the long term reliability of the circuit. In order to detect these faults recourse has been made to the use of current based test methods, which measure the “off-state” current, a value above the norm indicates the presence of a fault in the circuit. However, the advances in device technology has reduced the effectiveness of this approach by raising the “off-state” fault free current to values which make the discrimination between faulty and fault free circuits difficult. Several techniques have subsequently been developed to extend the useful range of current based test methods in a background of normally high “off-state” current. These techniques can be used to good advantage in testing SoI circuits at high temperatures, the particular method being adopted is called “current ratio” method. The only slight disadvantage of using current based testing methods with SoI circuits is that the test time will be protracted. Success Factors: - Understanding of test methodologies will ultimately enhance reliability. End Users: - Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc. - Manufacturers of semiconductors for HT applications.
To demonstrate fully the applicability of the BIST schemes for both memory and logic functions the design of a commercially available 8-bit microcontroller incorporating these test strategies was undertaken. This circuit was also chosen as CISSOID had designed a version of this microcontroller. In the demonstration vehicle the 8-bit microcontroller was combined with 32K x 8bit memory block. The overheads incurred by the test scheme amounted to a few percent. The results from the incorporation of both logic and memory BIST into a single chip 8-bit microcontroller with integrated memory (8 x 32K) would be of interest to semiconductor manufacturers, IC design houses, SoC and SIP designers, also to users of microcontrollers.
The SoC architecture used in this project to implement the demonstrator chip is relatively complex requiring the application of diverse strategies, both for production and field test of the memory and logic blocks. In many SoC designs the capacity of the memory blocks is such that they occupy in excess of 50% of the chip area and consequently the incorporation of BIST (Built in Self Test) incurs negligible area overhead. However in this instance the capacity of the memories is very small, amounting to two 32 x 16 and two 256 x 16 bit memories, consequently the design of a low area overhead BIST scheme is not only of paramount importance but also very challenging. In order to reduce area overheads a shared BIST scheme has been adopted in which the BIST Controller, Timing Generator and Address Counter is shared. The resulting area overhead is only approximately 10%. A BIST architecture to test the logic core has also been developed; initially using commercial tools incurring an area overhead amounting to 24%. However, an in-house scheme has been developed, namely BLTSCAN, which is also compatible with Boundary Scan Standard IEEE1149.1 and incurs an area overhead, which is approximately 50% less. The outcome of implementing this built in meomory test scheme would be of interest to IC design houses, IP core designers, SoC and SiP designers; particularly if they are using small embedded memories.
An important factor in ensuring product reliability is the effectiveness of the test strategies developed to identify defective circuits. In developing an effective test strategy is necessary to understand how various defects, which for example occur in the manufacturing process, affect the electrical behaviour of the circuit so that fault models can be created. These fault models are subsequently used by design automation tools to generate effective and efficient test patterns to detect the presence of defective circuits. Applicability of fault models for low and high temperature testing must also be considered in this instance. The result of the survey indicated that since a generic CMOS process is being used for both memory and logic circuits, although implemented in SoI, will, in general, be susceptible to similar fabrication defects as occur in logic/memory circuits implemented in standard bulk CMOS, hence will be detectable using current and voltage test methods. For high temperatures the main failure mechanisms to be considered are electromigration, time dependent dielectric breakdown and “hot-electron” effects. However, it has been noted that time dependent dielectric breakdown and “hot-electron” effects are not too dependent upon temperature leaving the main failure mechanism to be due to electromigration which manifests itself as either a short or an open circuit, which can be detected using current and voltage test methods. Success Factors: - Understanding of failure modes will ultimately enhance reliability. End Users: - Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc - Manufacturers of semiconductors for HT applications.
A complete study about behaviour and capability in DC mode for the LDMOS transistors integrated in UCL thin film SOI technology was performed. ATLAS simulations were realized and the simulations results were confirmed qualitatively by measurements over experimental UCL LDMOS. So, we are able to determine the optimal sizes of geometrical parameters such as drift and field plate lengths and also the optimal drift doping. In conclusion, we have shown that the buried oxide thickness and physical phenomena such as kink effect and quasi-saturation impose a doping choice, which considerably reduces the breakdown voltage (about 20V) in classical LDMOS with UCL thin film SOI process. In another hand, this way of optimizing such thin film SOI devices working is a very cheap manufacturing solution on basic UCL process. To go further, new structures are under investigation.
To speed up the design process, a library of basic analogue cells is needed for the XI10 SOI technology. Therefore, a variety of useful cells - band-gap circuits, comparators, operational amplifiers, oscillators, charge pumps, ADC, DAC - have been developed and characterised in the extended temperature range from -40C to 220C. The best of those were selected and formed into a design library including information on their performance (data sheets). They are now part of the X-FAB design kit XI10 and are usable outside the consortium also.
The design and high temperature (>200°C) digital device required a different approach. The technology required is SOI (Silicon On Insulator) and the design flow must be aware of the extended temperature range. The step that needs the most attention is the simulation: the models required for the low level components (FFs, gate, ram) have to be coherent with the behaviours at very high temperature (in "normal" designs, the worst case is the behaviour at temperature of 125°C as required by automotive specifications). This difference in the simulation phase leads to a different solution to modify the design during the many design iterations. This know-how will be useful to speed-up future digital design concerning high temperature designs.
The BOST scheme, which is incorporated in the tester/oven interface, will emulate the test strategies to be used to test embedded memories in SoCs. The test stimulus is derived from programmable function blocks ensuring that the test scheme is flexible and easily modified to accommodate the changes in test algorithms for the different types of memories incorporated in SoCs, ie SRAMs, DPRAMs and EEPROMs. The main test algorithm being used is called, generically, MARCH Test and is widely used in industry. The March test algorithm can detect all Address Faults, Stuck-at Faults, Transition Faults and Coupling Faults and has a complexity of O (10n), where n is the number of cells in the memory array. The algorithm can readily be modified to test Word Oriented Memories (WOM) by substituting the bit read/write commands in the March elements by word operations. The March test is also combined with IDDQ test methodologies in order to detect faults in the circuits, which are elusive to voltage test methods. The particular variant of IDDQ testing used is current signatures and ed. VIs have been developed to determine the maximum value of the fault free current to be used in the current signature method. Success Factors: - Understanding of test methodologies will ultimately enhance reliability. - Cost reduction in manufacture. - Cost reduction in digital ATE and reliability test equipment. End Users: - Designers for microelectronic systems to be used in HT applications in automotive, aerospace, oil exploration etc. - Manufacturers of semiconductors for HT applications.
Within the ATHIS project EEPROM development has been started at X-FAB with support by IMMS. First it was checked whether the XI10 SOI technology is suitable for the development of EEPROM. This has been found to be so, as only few additional process steps are necessary. The development was concentrated at the beginning on finding the optimum process modification and the most suitable EEPROM memory cell layout. For this a large number of different cells on wafers with process variations were realised and tested. Apart from the basic cell development, peripheral circuits for an EEPROM have been realised such as charge pumps, oscillators and HV switches. A novel layout for the basic EEPROM cell has been developed. German and international patents for this cell are applied and pending. Data endurance and retention tests on a double EEPROM cell in the extended temperature range (up to 250C) were successful passed. Initial measurements on a 32x16bit EEPROM prototype show promising results.