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Content archived on 2024-05-27

DISTRIBUTED PBX DEVELOPMENT SYSTEM WITH LAN INTERCONNECTION

Objective

The DIPSYLAN (Distributed PBX with LAN interconnection) is a single contractor first user action (FUSE) project. The duration of the project was 14 months (September 1st, 2000 until October 31st, 2001). Global Digital Technologies SA (GR) (GDT) is the coordinator of the project. According to the FUSE framework, GDT subcontracted technology provision and transfer activities to SIDSA (ES) and NTUA (GR).

The objective of DIPSYLAN is to enhance GDT?s technical capabilities and business process in such way that, by the end of the project, the design, development and delivery of complete prototypes of telecommunications subsystems comprising of both hardware and software would be possible.

The focus of DIPSYLAN was in the acquisition of know-how for the development of H/W subsystems and in the adoption of correct business processes for the cost-effective production of prototype and small volume H/W subsystems (at printed circuit board level).

OBJECTIVES
The DIPSYLAN project objectives are summarized as follows:
- Acquire technology in the area of H/W design and prototyping;
- Optimally use the acquired technology through the revision of the company's business process;
-Carry-out the DIPSYLAN baseline project (DeReGate)

DESCRIPTION OF WORK
The baseline project designed a low cost, compact system with H/W and S/W prototyping capabilities, able to support the development of SOHO communications applications (Intelligent NT, Small PBX, Router, Information gateway etc.) The board integrates the necessary processing capacity and interface support to facilitate S/W development and integration, as well as prototype application demonstration under realistic configurations and system conditions. Low cost and realistic system configuration was achieved with the integration of state of the art components (mainly from Infineon Technologies AG).

The board is easily extendable and different interface configurations can be supported. DeReGate can function as a "proof of concept" demonstrator for system level definition and application S/W integration for future IC products.

The DeReGate embeds the following interfaces:
2 Ethernet 10/100 BASE-T interfaces.
2 UART interfaces (1 multiplexed with IrDA).
1 ATM UTOPIA (Level 1/Level 2) interface.
2 Analogue (t/r) telephone interfaces.
2 ISDN S/T interfaces.
3 ISDN Up interfaces.
1 PRI interface (E1/T1).
1 SHDSL.
1 USB host/device
Extension connectors:
4 x PCM
1 x IOM-2000
1 x IOM-2
1 x ?P bus

Fields of science (EuroSciVoc)

CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.

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Topic(s)

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Funding Scheme

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DEM - Demonstration contracts

Coordinator

GLOBAL DIGITAL TECHNOLOGIES S.A.
EU contribution
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Address
EIRINIS AVENUE 65
48100 PREVEZA
Greece

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Total cost

The total costs incurred by this organisation to participate in the project, including direct and indirect costs. This amount is a subset of the overall project budget.

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