Objective
The exponential scaling down of silicon circuits obtained during the last decades is expected to continue for the next 15 years, leading eventually to random-access memories (DRAM) with a density of almost 20 Gbits per cm2. This will require fabrication of VLSI circuits with a minimum feature size of 100 nm. Below this critical size, even if fabrication at ~35 nm proves in the near future to be practical, the implementation of 64 Gbit and 256 Gbit DRAM generations is questionable mainly because of the scaling down of charge storage capacitors. As an alternative, the fabrication of new nanomemories should be investigated. The goal of this project is to fabricate a new Ge nano-crystals based memory which utilizes direct tunnelling and storage in the Ge islands. The advantage of the process is the use of Focused Ion Beam (FIB) nano-patterning of the substrate to precisely control (at the nm level) the islands size, shape and positioning. The exponential scaling down of silicon circuits obtained during the last decades is expected to continue for the next 15 years, leading eventually to random-access memories (DRAM) with a density of almost 20 Gbits per cm2. This will require fabrication of VLSI circuits with a minimum feature size of 100 nm. Below this critical size, even if fabrication at ~35 nm proves in the near future to be practical, the implementation of 64 Gbit and 256 Gbit DRAM generations is questionable mainly because of the scaling down of charge storage capacitors. As an alternative, the fabrication of new nanomemories should be investigated. The goal of this project is to fabricate a new Ge nano-crystals based memory which utilizes direct tunneling and storage in the Ge islands. The advantage of the process is the use of Focused Ion Beam (FIB) nano-patterning of the substrate to precisely control (at the nm level) the islands size, shape and positioning.
OBJECTIVES
The objective of the project is twofold : i) to develop and assess the potential for FIB nano-patterning for the microelectronics requirements in the sub 10 nm domain and ii) to demonstrate new generation of nano-crystals memories with potential mass fabrication and full compatibility with CMOS technology. These two goals that correspond to industrial challenges, will be achieved in collaboration with the two companies involved in this project. This collaboration will favor the tranfer of technology between research groups and industry trying to approach manufacturable devices. Combination of FIB nano-patterning and natural formation of Ge islands will permit to circumvent most of the problems induced by self-organisation (non reproducible device characteristics) with a fabrication process of device structures with minimum perturbation of the conventional MOS transistors technology.
DESCRIPTION OF WORK
The work will be divided in 5 major tasks:
1) nano-patterning of the substrate by Focused Ga+ Ions Beam at the nanometer scale. The aim of this task is to realise uniform array of sub-10 nm holes on large scale areas. The influence of the process parameters on the induced damage will be measured. Experimental conditions will be optimized to reduce the silicon surface degradation, lower the holes sizes and precisely control the holes shape and positioning;
2) restoring of the substrate by thermal annealing in ultra-high vacuum. Investigation will focus on the conditions for soft thermal annealing to guarantee total removal of crystalline defects and desorption of Ga implanted atoms without modifying the holes shape/size. At this step appearence of high index facets on the holes sides is expected. Facets angles will be varied by modifying the aspect ratios (height over lateral size) of the holes;
3) fabrication of an array of isolated Ge quantum dots (QD). Nucleation of Ge islands in the holes will be first investigated by in-situ STM in order to determine the experimental conditions of Volmer Weber growth (selective nucleation of islands). Growth process will then be transferred to MBE and LPCVD growth techniques. The characteristics of the Ge QDs arrays obtained by the different growth processes will be compared and analysed;
4) fabrication of the tunnel oxide (between the Ge islands) and of the control oxide. They will both be performed by in situ thermal oxidation to ensure a good quality oxide layer. The tunnel oxide fabrication is based on the different rates of oxidation of Ge and Si and on the oxide penetration from the edges of the islands to the Ge/Si interface. Ge/SiO2 demixion effects are also expected to occur in agreement with previous experimental results;
5) device memory fabrication and electrical characterization. The gate, source and drain regions of the MOSFET device will be fabricated using conventional 0.6 microns MOS process.
Funding Scheme
CSC - Cost-sharing contractsCoordinator
75794 Paris Cedex 16
France
Participants (7)
5651 GG Eindhoven
52425 Juelich
69621 Villeurbanne Cedex
15310 Aghia Paraskevi Attikis
92120 Montrouge
00173 Roma
1678 Nicosia
