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Contenido archivado el 2024-05-24

Ultra Low K Dielectrics For Damascene Copper Interconnect Schemes

Objetivo

This project is focussed on the most critical aspects of the back end interconnection field for 100 nm CMOS technology: ultra low k (k<2.2) dielectric materials and integration processes with copper as interconnect metal. Both single and dual damascene modules will be prepared with selected low k porous materials as dielectric and electrically characterized with respect to their k values. The assessment of a copper- low k RF demonstrator will be one of the challenging aspects of this project. Electrical simulation of a full CPU ASIC will be carried out with the characteristics of low k dielectric structures obtained within the consortium to predict the impact of ultra low k dielectrics on the enhancement of device performance. Thermal properties of the low k materials and the interconnect system are analysed. A dielectric and metal reliability database will be established for industrial use comparing ultra low k structures to copper-oxide modules.

Objectives:
Among the broad research activities needed to achieve interconnects for 100 nm CMOS technology, the ULISSE project concentrates its effort on the most critical aspects of the back end multilevel interconnection field: development and feasibility evaluation of ultra low k dielectric integration processes with emphasis on the reliability issues. The main objective of the project will be to achieve an integrated process using a low k material with k< 2.2 and copper as metal interconnection. In order to address the requirements of real products ULISSE will focus on two major kinds of CMOS technology RF components and digital components. The preparation and assessment of a Cu/low-k RF demonstrator including an on-chip inductor will be one of the very challenging project goals. Digital components assessment will be carried out with electrical simulation of an ASIC CPU (60 millions of transistors and 6 metal interconnect layers).

Work description:
WP1 define the evaluation procedure, methodologies and criteria of choice of low k (k<2.2) dielectric materials and processes for integration.
In WP2 work package, basic steps for ultra low k materials processing are developed. To achieve a dielectric value of k<2.2 requires the introduction of porosity as a major constituent of dielectrics. The chemical, mechanical, electrical characterizations of many materials will result in a selection of porous dielectrics suitable for integration with copper metal at to+9. The low k related patterning issues will be addressed: choice of integration architecture, development of the etch and post etch residues removal process steps.
WP3: Ultra low k material integration in damascenes architectures. The compatibility of metal barrier materials with porous dielectrics is first investigated. Then the compatibility of Chemical Mechanical Polishing steps with porous materials -a challenging aspect- is studied. Dual damascene modules are used to assess yield and measure electrical demonstrators of the integrated structure. An RF demonstrator device employing copper inductors and ultra low k dielectrics in single damascene structure is proposed once the main issues of materials and its integration have been solved.

The objectives of WP4 work is to address, at the early stage of material development, the performance and reliability issues when new dielectric materials are introduced in interconnects modules. The impact of poor thermal conductivity of porous dielectrics is analysed. The impact of low k values on the performance of two demonstrator components is addressed: electrical simulation of a full CPU die and RF properties of the ultra low k RF demonstrator. Copper drift diffusion in the dielectrics, measurement of leakage currents between interconnection lines, electromigration and stress migration failures induced in metal are investigated versus capping and barrier layer characteristics.

Milestones:
M1 Definition of methodologies and criteria of choice of low k dielectrics, to+3
M2 Selection of k<2.2 porous dielectrics and deposition methods for integration, to+9
M3 Preparation and assessment of 2 demonstrators: 1) dual damascene modules to achieve effective k values of dielectrics needed for simulation of a full ASIC CPU, 2) RF demonstrator including an on-chip copper inductor and ultra low k porous dielectric, to+21
M4 Establishment of a reliability data base for industrial use, to+ 24

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Coordinador

COMMISSARIAT A L'ENERGIE ATOMIQUE
Aportación de la UE
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Dirección
31-33 RUE DE LA FEDERATION
75752 PARIS CEDEX 15
Francia

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Participantes (6)

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