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Content archived on 2024-05-27

Quantum Tunneling Device Technology on Silicon


The subject of this proposal is the design and fabrication of negative-differential resistance (NDR) devices on silicon substrate. The objective is a theoretical and experimental assessment of emerging NDR technologies providing a robust and manufacturability device operation on the nano-scale. The monolithic combination with suitable 3-terminal devices on Si substrate will be elaborated. This combination allows the realisation of novel high speed and digital circuits based on architectures implementing negative-differential resistance devices. Based on this technology both novel circuit families like the hardware implementation of advanced re-programmable neurons as well as a quantitative performance improvement is aimed at.

QUDOS will make a robust negative-differential device technology on the available on a Si-substrate. The manufacturability, compatibility to Si circuitry, and performance of promising emerging candidates will be quantitatively elaborated. The benefit of this outstanding device functionality will be implemented in novel circuit architectures providing an ultra-high speed receiver, and a threshold logic gate. The latter approach will enable re-programmable advanced neurons. Their large-scale future hardware implementation will be studied in detail and quantitatively compared to present software implementations.

On a silicon substrate both the Si/SiGe and the III/V material system is experimentally studied towards a manufacturability NDR device. The low growth temperature of the molecular beam epitaxy enables abrupt doping interfaces for inter-band tunnelling diodes (ITD). This approach will be scaled down to the nm-range by self-assembled Ge-dots incorporated in the tunnelling layers aiming at a higher current density at a reduced capacitive load. A novel design of a SixGe1-x quasi substrate enables a stress dependent conduction band discontinuity at the barrier/well interface for resonant tunnelling diode (RTD) operation.
This approach is aiming at an even more reduced capacitive load and a higher temperature budget for a more flexible co-integration with Si circuits. Recently nano-meter scale pre-pattering treatment of Si-substrate enables the growth of high quality InP-buffer layers and consequently the first successful demonstration of a III/V RTD on Si. This approach aims at the availability of their outstanding speed performance for co-integration with Si circuits. The potential of these approaches will be checked against robustness and technological needs for co-integration using an appropriate circuit architecture and demonstrator. Based on technological data a high-speed latch, a threshold gate and a re-programmable neuron will be developed and tested.


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