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Quantum Tunneling Device Technology on Silicon

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Hardware implementations of re-programmable neurons

The ability of artificial neural networks to learn and generalise complex relationships from a collection of training examples has been established through numerous research studies. A new architecture of programmable logic gates aims to provide for the training and reconfiguration of their hardware realisations.

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The problems associated with the scaling limits of Complementary metal-oxide semiconductor (CMOS) devices have led to the search for alternative transistor and circuit configurations. Proposals for silicon-based technologies include single electron devices, resonant-tunnelling diodes (RTDs) and metal-oxide semiconductor field-effect transistors (MOSFETs). Of these, RTDs appear to hold the most promise as a short to medium-term solution offering the possibility to improve compactness and speed of very large-scale integrated (VLSI) circuits. Research work within the QUDOS project aimed to bridge the current gap between research on functional devices based on RTDs and research into logic synthesis for field-programmable gate arrays (FPGAs). FPGAs consist of logic, input/output and routing elements, which can be programmed and reprogrammed in the field to customise FPGAs, enabling them to implement a given application in milliseconds. With the development of large and highly parallel FPGA circuits, hardware realisations of artificial neural networks (ANNs) with enhanced speed of operation and portability have become possible. This particular application was chosen by QUDOS project partners as the future success of RTD-based threshold logic gates (TLGs) will depend on their suitability for use in VLSI circuits. The need for reliable and repeatable manufacture of such devices that display suitable performance characteristics is obvious. Gate design must also demonstrate a robustness that will be tolerant of device parameters and power supply variations. The programmable TLG, designed to realise all possible binary functions for any number of inputs was incorporated (along with EX-OR and AND gates) in a positive Davio expansion architecture. In addition, multiple-valued logic (MVL) weights as 'soft' parameters representing voltages allowed all binary functions to be programmed when the TLGs were arranged in an appropriate architecture. A parallel architecture, similar to that required for the ANNs, was considered by connecting multiple two-input programmable TLGs and the independence of their programmable functions was investigated. The outcome suggested that programmable TLGs can be connected in larger scale circuits; however, they appear to be more suited to highly parallel architectures.

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