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Contenido archivado el 2024-05-24

A/D converter in superconductor-semiconductor hybrid technology

Objetivo

We propose the realization of a hybrid A/D converter made of a high-Tc superconductor (HTS) modulator chip and cooled GaAs or InP chips for the amplifier and high-speed digital filter stages. The modulator, which is the most important speed-bottle-neck in semiconductor A/D converter designs, is a very simple circuit in HTS technology, which takes full advantage of the speed superiority of RSFQ circuits over conventional semiconductor circuits. The more complex digital filtering parts of the converter are implemented in cooled semiconductor circuits. The performance of GaAs/InP/CMOS chips is significantly increased at lower temperatures. We propose the realization of a hybrid A/D converter made of a high-Tc superconductor (HTS) modulator chip and cooled GaAs or InP chips for the amplifier and high speed digital filter stages. The modulator, which is the most important speed-bottle-neck in semiconductor A/D converter designs, is a very simple circuit in HTS technology, which takes full advantage of the speed superiority of RSFQ circuits over conventional semiconductor circuits. The more complex digital filtering parts of the converter are implemented in cooled semiconductor circuits. The performance of GaAs/InP/CMOS chips is significantly increased at lower temperatures.

OBJECTIVES
The objective is to demonstrate the performance edge of an A/D converter hybrid circuit, consisting of a super-conducting over-sampling sigma-delta modulator followed by a semiconductor digital (decimation) filter. A second objective is to demonstrate a (minimum) bandwidth-precision performance of 120 MHz (Nyquist frequency) - spurious-free dynamic range (SFDR) corresponding to 16 effective bits. The third objective is to fill a technology gap, "Moore/s law for semiconductor A/D converters" (as shown in a recent survey by R Walden, Hughes Research Laboratory) indicates that conventional A/D converters with this performance will not exist within the next 10 years. The problem is that A/D converters with this performance are needed NOW for advanced radar and wide-band mobile radio communication systems.

DESCRIPTION OF WORK
An HTS sigma-delta modulator chip will be designed, simulated and manufactured at U Twente and Chalmers. A high-Tc superconductor modulator with 170 GHz sampling rate has been demonstrated at the University of Twente). The very high-speed semiconductor circuit interface will be specified at Chalmers and fabricated in cooperation with the University of Duisburg.
An amplifier chip in InP technology will be designed, simulated and manufactured at Chalmers. A CMOS digital (decimation) filter will be designed by Ericsson MIC and manufactured by an Ericsson subcontractor. The interconnections are critical to the overall performance of the ADC hybrid, as the amplitude of the SFQ pulses is only a few milli volts and their width is 1-2 picoseconds. Two technologies, flip-chip and closely-packed multichip module, will be evaluated by THALES for high speed transmission of the these pulses from the HTS chip to the read-out electronics. On chip testing is a highly non-trivial task at the very high (10-15 GHz) bit rates of the modulator, but it can be done with comparatively simple dedicated circuits, even using DC measurements. The clock pulses will be generated either by an external oscillator and fed into the system via an RF port, or by an SFQ pulse generator integrated on the super-conducting chip and with an amplifier to provide a clock output to the external electronics via an RF output port. Cryo-packaging needs a special attention. Air Liquide will adapt one of their top-of -the-line Stirling coolers for the project. The goal is to demonstrate and evaluate a fully cryo-packed ADC module with an integrated cooler.

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Coordinador

CHALMERS TEKNISKA HOEGSKOLA AKTIEBOLAG
Aportación de la UE
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Dirección

412 96 GOETEBORG
Suecia

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Participantes (6)

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