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Deliverables
This result consists in methodology and software dedicated to extraction of compact models for on-chip passive structures with high frequency electromagnetic field effects, such as: skin effect, current crowding, induced voltage, propagation delay, cross-talk, charge relaxation, etc. It is dedicated to analog/RF/wireless chip and electronic system designers. It can be also used to build model libraries for new (nano) technology design kits.
The methodology is based on the original "All Levels Reduced Order Modelling (ALLROM)" and "Very Fast Simulation (VFS)" strategies, described in details in [D8], [D11] and [D16]. ALLROM consists in a series of ROM techniques, which can be applied successively and/or alternatively at several stages:
- Macro modelling (CellHO = Cell Homogenisation, ELOB = Equivalent Layer of Open Boundary Condition, dFIT = dual Finite Integrals Technique),
- Apriori (PROM = Phenomenological based ROM, CROM = Coarsest ROM based on lumped circuit having equivalent energy,
- TCR = Tree/Cotree Reduction and MEEC = Magneto-Electro Equivalent Circuit), "on the fly" (FredHO = Frequency dependent Hodge Operators, ASPEEC = Algebraic Sparcefied Partial Equivalent Electric Circuit, BANESSA = Branch and Nodes Elimination by Symbolic Successive Approximation) and
- Aposteriori (KROM = Krylov based ROM, TBR = Truncated Balanced Reduction of semi-state/descriptor systems, Avectorfit = automated frequency Characteristic fitting by vectorfit).
The embedding of ROM techniques in the early electromagnetic modelling stages is extremely efficient, allowing the reduction of DOFs number up to 10 million times.
The VFS strategy has a complementary aim, to reduce the time required for simulation and compact model extraction.
It consists in a series of acceleration techniques, such as:
- AFS = Adaptive Frequency Sampling,
- TLTM = Transmission Line model based on Transversal Magnetic Field with interpolated frequency dependent p.u.l. parameters,
- FTS = Frequency vs Time domain or Semi-space state simulation
- PDS = Parallel or Distributed Simulation.
By this strategy, the simulation time was reduced up to 10,000 times, to 20s in simple cases and <1000s for complex structures. The software is written in C++ and was tested under Linux OS. It complies EDA/TCAD standards, in order to be easily integrated in several design environments.
The input files describe layout and technology in standard formats (such as .cif and. sipp).
The output files contains the compact model of the device in SPICE format, as well as other numerical or graphic results (.snp, .vtk, Smith diagram, lumped or p.u.l. parameters, quality factor, etc.) very useful in the design process.
The code has following main features: import, load, save, interactive graphic edit, solve, simulate, reduce order and Spice model synthesis.
The methodology and software were benchmarked against measured data for Codestar standard test structures: meander resistors, capacitors, spiral inductors, interconnect/transmission lines, and challenging structures: coupled inductors, LC cells.
The simulation results over 0-40GHz frequency range have an accuracy better then 5% in standard cases, and better than technological errors for challenging cases.
There is also available a software toolbox called ¿ROM Workbench¿, developed in Matlab and compiled under Linux. It can be used to decide which ROM technique is the most appropriate for the reduction of models, obtained from the electromagnetic field analysis. Its aim is to allow the user to reduce models by means of as many state of the art ROM techniques as possible, and to compare the results.
The ROM workbench consists of:
- A series of benchmark problems;
- A set of model order reduction methods;
- Criteria for results evaluation and comparison.
To start with the workbench, a system description generated by one of the field solvers is used. Such an output can be either a linear time invariant system described by means of semi-state space matrices, or the frequency characteristic described by the variation of the impedance, admittance or S-parameter matrices with respect to the frequency. The reduction can be carried out by means of various methods.
These methods include:
- Explicit moment matching,
- Krylov subspace techniques,
- Laguerre techniques,
- A two-step Lanczos strategy,
- Also a new two step reduction strategy, based on a PRIMA technique followed by a truncated balanced reduction,
- Truncated balanced realisation procedures.
A very robust technique included in the ROM Workbench is the vector fitting method. The workbench is able to check the passivity and to compare the reference model and the reduced one, either on the time responses (step, impulse, etc.) or on the frequency responses (Bode, Nyquist, Smith, etc). Lumped parameters, quality factors or line parameters can also be compared.
The scientific result has been (published) knowledge on the integration of complex mathematical software in a cooperative library of components. This library of components has been made available on a cd-rom (status confidential) to all partners. Dissemination: Several publications. Result potential: The increased insight in the integration process will (so we hope) eventually lead to a more automatized integration process. At its turn, this will then reduce the effort required to let complex scientific software cooperate. The result is used in research: For Industrial (PhD) projects -- where multi-physical problems mostly require software integration and is further used for education (courses Numerical Programming 1 and 2).
A novel model order reduction technique has been developed, tested and implemented. It uses Laguerre expansions as the basis, and intermediate orthogonalisation after each iteration rather than at the end of the iterative process (like in the SVD-Laguerre method). It is necessary to sometimes perform the orthogonalisation twice, in order to ensure optimal orthogonality. The latter is essential when the resulting models are being used for time domain simulations.
The new robust and efficient Laguerre method with intermediate orthogonalisation (developed within the present project) has been tested extensively within the Philips in-house code Fasterix. Tests have been carried out first outside of this programme, but due to the extremely favourable results especially in time domain simulations (which were unstable with the old method) it was decided to implement the method directly into the software.
The method is not restricted to applications in the electronics industry, but can also be applied in many other areas where model order reduction is required. In this respect, it is a very general technique.
The Codestar solver allows to analyze and predict the high frequency performance of advanced interconnect architectures. The required input consists of interconnect geometry (layout, wire dimensions, dielectric thickness), material properties (wire resistivity, dielectric constant and loss tangent) and frequency range of interest.
The provided output is in form of S-parameters or line parameters RCLG per unit length, in function of frequency.
The output allows to predict the interconnect bandwidth in function of the choice of the conductor and insulating materials, and in function of interconnect dimensions. Therefore, it is possible to evaluate the impact of new materials and new technology nodes on signal propagation on ICs.
The further capability to generate a reduced order model based on lumped elements and consistion of a Spice netlist, allows to virtually model any type of interconnect architecture and to analyse its behaviour in time domain.
This opens the possibility of performing "what if" experiments in a short time without having to wait for structures to be implemented on silicon; in many cases, this implementation is made very difficult by very aggressive dimensions and complex architectures. The possibility to predict the interconnect performance allows to evaluate the impact of future technology nodes on signal propagation on ICs.
This type of activity is in the framework of the Imec research program on Advanced Interconnects.
In general, IMECs advanced CMOS research targets technology nodes at least two generations ahead of industrial needs. These research activities focus on new materials, process steps and modules, and the demonstration of novel device architectures. The activities are aligned with the overall timing and objectives of the International Technology Roadmap for Semiconductors (ITRS). IC manufacturers, tool and materials suppliers participate in the research programs.
The Advanced Interconnect program focuses on the preparation of the selection of the interconnect technology selection for the 45 and 32nm node by:
a) Finding ways to meet ITRS RC delay specs
- Integrating low-k materials with k < 2.7 and exploring the feasibility of air gap technology
- Investigating mechanisms that determine copper resistivity in narrow dimensions
- Evaluating dielectric reliability, barrier integrity, electromigration and stress induced voiding
b) Developing packaging solutions compatible with Cu/low-k
- Fine pitch wire bonding
- Fine pitch flip chip solutions
- Evaluate reliability of packaging solution
c) Developing above IC interconnect functionality
- Wafer Level Packaged multi level interconnects for high speed signal routing
- Wafer Level Packaged passive components
d) Exploring Novel Interconnect Technologies
The results of the Codestar activity fit in d), but have strong implications in a), b) c) for the performance prediction.
The continual need for a more accurate description of devices in electrical and electro technical engineering leads to increasingly larger models. Hence, a need arises for reduced-order modelling allowing downsizing large initials models to more tractable formats that can then be used as black box elements in subsequent simulations. In our case we typically consider large state-space descriptions arising from the numerical solution of Maxwell's equations and the reduced models are needed for use in subsequent circuit simulations. The techniques used to obtain these smaller models are the so-called Model Order Reduction (MOR) techniques. Various MOR-techniques have been developed in the past either based on balanced realization algorithms or on projection based Krylov-subspace methods. The best-known techniques are (several variants of) PVL (Pade via Lanczos)), block Arnoldi and passive reduced-order macro modelling or PRIMA.
In the CODESTAR project a completely new MOR-technique based on the use of Laguerre functions was (further) developed. This technique has been published under the name Laguerre-SVD or LSVD. This technique offers several advantages over other techniques, in particular its stability at both the low and high frequency end and its guaranteed passivity. In the CODESTAR project LSVD was applied to and combined with a state-space description of interconnect structures obtained through an FDTD-like discretisation of the problem space whereby the spatial derivatives are discretised using the typical arrangement of the field components in Yee-cells but leaving the time derivative intact. It has been shown that the LSVD technique is capable of reducing large system spaces (more than half a million variables) to systems not exceeding 100 variables.
Further research is under way showing that specialised versions of LSVD can be developed applicable to discrete frequency bands, so-called band-limited model order reduction. Such a technique would be particularly useful to describe resonant systems.
This result consists of a software tool that is now commercially available. The software extends the existing capabilities since it allows for a full treatment of the Maxwell equations together with the Ohm's law in metals (this is still conventional) but also consistently with the drift-diffusion model for semiconductors. The result has been the motivation for setting up a spin-off company that will take care of the sales and customer support as well as the further development of the tool. As such the company has now 5 persons employed. A business plan has been created and the company is presently in search for venture capital to realize the set up of the market channels.
"Development of an RF-test-chip for the Benchmark case".
The task was to implement passive structures (like resistors, capacitors and inductors) for simulator benchmarking. The realized structures were close to the recent requirements of foundry customers. This way real-life solutions could be tested both on the measurement and electromagnetic simulation sides. For the Parties involved in the simulations it was necessary to obtain as accurate measurement data as possible.
This was achieved by s-parameter measurements with industry-standard calibration techniques including open-short deem bedding. The technology data was collected on the basis of in-process control (MAP or PCM) statistics. A few key parameters were also verified by measurements on a special (capacitor) test-chip. It included dedicated structures in order to double-check diverse oxide and metal layer thickness. This additional option to the Project confirmed an excellent agreement with the MAP data on the particular wafer. In addition to the standard benchmark scenarios a set of advanced structures were also provided. Among these designs were basic spiral-capacitor tank circuits, coupled inductors and diverse galvanic substrate connections to test various EM shielding techniques.
The test chip was implemented in a state-of-art 0.35um BiCMOS SiGe HBT technology developed by Austria Microsystems. All data like s-parameters from the different devices, GDS layer information, technology parameters and the relevant textual explanation were provided for the CODESTAR project in a consistent manner. The scheme preserved the coherency of the various information types and made it possible the safe and easy identification of the selected items.
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