Objective
The ADAMANT project aims to investigate the feasibility and competitiveness of the "Discrete-Trap" storage mechanism, for future generations of stand-alone and embedded Non Volatile Memories. Research and development carried out in the project will address the 100nm Flash Technology node and prepare the 80nm generation.
The main objectives will be:
- Study the two most promising technological solutions for discrete-traps storage nodes (e.g. nano-islands of semiconductor materials and continuous natural trapping layers);
- Evaluation of single memory cells based on discrete-trap storage nodes;
- Development and characterization of large memory arrays (from Kbit to Mbit) based on discrete;
-trap storage nodes;
- Development of comprehensive and predictive modelling.
Objectives:
The ADAMANT project aims to investigate the feasibility and competitiveness of the "Discrete-Trap" storage mechanism, for future generations of stand-alone and embedded Non Volatile Memories. Research and development carried out in the project will address the 100nm Flash Technology node and prepare the 80nm generation.
Work description:
The ADAMANT project focuses on memory innovation, with the aim to investigate the potential of the "Discrete Trap" storage mechanism to guarantee the continuous Flash cell scaling beyond the 80nm technology node.
The work within ADAMANT will involve four closely connected activities:
I. Engineering of discrete-trap storage nodes - Nano-islands of semiconductor materials (Si-dots, SiN-dots), fabricated by state-of-the-art LPCVD, will be studied by some partners. Other partners will develop and optimise continuous natural trapping layers (LPCVD-Si3N4, ALCVD-Al2O3);
II. Evaluation of single memory cells based on discrete-trap storage nodes - Discrete-trap storage nodes will be integrated in 1-transistor and 2-transistors memory cells, using advanced technologies (0.18-0.1µm) and scaled tunnel oxide (<7nm). An in-depth electrical characterization of memory cells will be performed to clearly define the optimum program/erase conditions for Discrete-Traps memories;
III Evaluation of large memory arrays based on discrete-trap storage nodes - Large memory array demonstrators (from Kbit to Mbit) with discrete-trap storage nodes will be fabricated. Emphasis will be done to the evaluation of statistical fluctuations of device characteristics and reliability issues. A theoretical architectural study to optimise array organization will be performed in view of future industrial implementation;
IV. Development of comprehensive and predictive modelling - Simulations of performances and reliability characteristics of memory cells and memory arrays based on discrete-trap storage nodes will be also performed, to optimise the memory cell architecture, to evaluate cell shrink ability potential, to develop extrapolation models for the reliability assessment of scaled industrial discrete-traps memory products.
Milestones:
M1. At T0+9 months: qualification of the discrete storage node materials and deposition processes and selection of best solutions for integration in the memory array demonstrator;
M2. At T0+18 months: assessment of the feasibility of a discrete-trap memory array;
M3. At T0+24 months: evaluation of competitiveness and development potential of Discrete-Trap based Non Volatile Memories.
Decision point for a further project aimed at the industrial implementation of these devices.
Fields of science (EuroSciVoc)
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
CORDIS classifies projects with EuroSciVoc, a multilingual taxonomy of fields of science, through a semi-automatic process based on NLP techniques. See: The European Science Vocabulary.
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Coordinator
75752 PARIS CEDEX 15
France
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