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High-Speed Three-Dimensional Chip-to-Chip Communication

Objective

We investigate interconnection techniques that improve the current situation interms of available pin count in 3D structures, communication bandwidth and dissipated power:
1. The study and implementation of 3D interconnection technology compatible with advanced ICs that supports the above. It is based on a wireless capacitive coupling between structures located in facing positions on two opposite Ics;
2. Since the performance of this kind of coupling is sensitive to the alignment of stacked chips, study and implementation of 3D alignment methodology of ICs will be carried out. This technology is based on the self-alignment properties of melted bumps due to surface tension. Another approach will be based on capacitive coupling between structures located in facing positions on two opposite ICs.

OBJECTIVES
1) To study and implement a 3D interconnection technology compatible with advanced IC technology that supports the above. It is based on a wireless capacitive coupling between structures located in facing positions on two opposite Ics;
2) Since the performance of this kind of coupling is sensitive to the alignment of stacked chips, study and implementation of a 3D alignment methodology IC will be carried out. This technology is based on the self-alignment properties of melted bumps due to surface tension. Another approach will be based on capacitive coupling between structures located in facing positions on two opposite ICs.

DESCRIPTION OF WORK
The idea consists of placing two or more ICs in a 3D stacked front-to-front configuration in such a way that a common surface between each pair of two opposite chip surfaces is created. The chip surface bears a two-dimensional array of micro-locations, possibly covered by a protecting material. Communication will take place by capacitive coupling using capacitors created at locations in the micro-array. In order to maximise the signal to noise ratio, tight chip alignment is necessary. The alignment will be performed either by exploiting self-alignment induced by melted bumps or through capacitive means using on-chip structures that provide feedback to the placement machines. This scheme is extremely compact in terms of area, since we expect to need no more than 40 sq. microns/pin versus a 1000 sq. microns required by the best technologies available today. In terms of dissipated power, it lowers the interchip capacitance significantly and thus the switching energy.

Packaging must ensure the device supports:
1. chip stacking, and;
2. external connectivity to common signals, power and global clock.
Packaging machines have to be able to place the ICs in a relatively precise way. We expect to demonstrate the feasibility of precise alignment using a simplified laboratory set-up. Chip-to-chip interconnections based on the above principles require silicon post-processing.

In particular, the following features will be sought:
1. Thinning of the top passivation in order to increase the capacitive coupling between adjacent layers;
2. Intra-chip vias based on silicon thinning and deep trench development to allow three-dimensional stacked structures and improve heat removal.

Funding Scheme

CSC - Cost-sharing contracts

Coordinator

ALMA MATER STUDIORUM - UNIVERSITA DI BOLOGNA
Address
Via Zamboni 33
40126 Bologna
Italy

Participants (2)

COMMISSARIAT A L'ENERGIE ATOMIQUE
France
Address
31-33 Rue De La Federation
75752 Paris Cedex 15
STMICROELECTRONICS S.R.L.
Italy
Address
Via Olivetti 2
20041 Agrate Brianza