Objetivo
The objective of this project is the development of a prototype system for the verification of behavioural correctness and testability of MOS VLSI design.
Both the top-down Boolean design phase as well as the bottom-up electricaland timing verification phase are envisaged.
New to this system is that an expert system (DIALOG) is used to reduce the enormous amount of simulation time traditionally used in design by zooming in into potential critical trouble spots in the design (guided simulation)based on good design knowledge.
Therefore the expert systems guides two Mixed-Mode simulators. One for top-down Boolean design covering RTL, functional, gate, switch level including assignable delay modelling (LOGMOS). Also a powerful fault-simulator with accurate fault models (FLOGMOS) has been developed.
The other simulators are a new electrical/switch level simulator (SWITCH) that includes device inpedance and charge sharing and a segmented wave form analysis simulator (SWAN) which is 20 to 50 times faster than SPICE, but has the same accuracy.
In order to communicate with this system the user has a procedural structural description language (HILARICS), a symbolic, connectivity based graphics editor that makes the compaction tool (CAMELEON), a procedural PLA,ROM generator (PLASCO).
The deliverables thus are in the form of set of programmes CAMELEON, PLASCO,HILARICS, DIALOG, LOGMOS, FLOMOS, SWITCH, SWAN.
Results:
All six reports have been received, the last covering the period till December 85. The project is now completed.
The contractors have not had any significant delays, but a small delay was reported on the database work because of underestimation of the effort required. Corrective action have been taken.
First phase test versions of all programmes have been built and have been tested by the industrial partners. DIALOG, LOGMOS, SWITCH and PLASCO have been successfully used for debugging, simulation and designing of VLSI chips. DIALOG experiments show the feasibility of an expert system for guided simulation while SWITCH shows performance improvements of 20 to 50 times with the respect to SPICE. The underlying principles of SWAN have been tested successfully and detailed transistor models have been entered in it. A first version of HILARICS has been interfaced to CAMELEON and new DIALOG whereby the knowledge base is built up using a PASCAL-PROLOG like language.
To date tools developed are integrated into the CATHEDRAL I Silicon compiler, together with other tools developed in ESPRIT project 97 and 1058.A new LISP environment LEXTOC for design style description has been implemented. Use of this language allows a remarkable circuit debugging speed of20000 transistor/hrs on a VAX 11/780. The design management system is embedded in CATHEDRAL I. The only fundamental differences in the outcome of the project are the extension of the packages currently in the system and the addition of a database prototype to the system.
Programa(s)
Tema(s)
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3030 HEVERLEE
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