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Procedures for the early phase evaluation of reliability of electronic components by development of CECC rules


The aim of this project is the improvement of the European CECC rules for the evaluation of the reliability of electronic components. This objective will be pursued by developing specific tools (test structures and testing methods) which will enable an evaluation of the reliability of electronic components within the manufacturing process. This would greatly decrease the costs related with qualification of finished products. In the present situation most European semiconductor manufacturers and design groups use different (mostly proprietary) test structures, measurement techniques, reliability evaluation procedures and prediction tools. This unavoidably makes data exchange both complicated and time consuming, and usually implies duplication of efforts and delays in the design/production cycle.
The project is directed towards a development of the CECC documents 00804 and 00805, which have been produced as a guide for the application of reliability requirements of electronic components within the EN 29000 system, which currently provides the rules for an organization's quality system. This is further specified by the EN W 190000-6, 'Procedures for approval and quality management'. In order to demonstrate the process capability within a total quality evaluation system, the above mentioned document recommends the use of suitable technology characterisation vehicles. These vehicles should enable the study of intrinsic reliability measurements, related to most commonly encountered IC failure mechanisms. The strong need for a written standard required by industry for the cost effective implementation of quality and reliability assurance schemes is testimonied by the large effort spent on the JESSI AC 41 Technology Assessment consortium. One of the outcomes of this project will be the availability of a common proposal describing automatically generated test structures and associated reliability assessment methods for main 0.5 uM CMOS integrated circuits failure mechanisms. This reliability documentation has been proposed as a standard to the CENELEC Standardization Organisation (Technical Committee 117, 'Electronic Design Automation'). In order to stimulate acceptance and usage of standard reliability test vehicles by the European Electronics industry, and to consolidate a written standard on the evaluation of semiconductor products reliability by means of these test vehicles further efforts are needed:
(i) the effectiveness of the testing methods must be validated through experiments, considering emerging technologies with feature size scaled to 0.35 um (ii) test structures and methods for validation of mixed bipolar/CMOS technologies must be included;
(iii) the set of considered failure mechanisms must be completed including, for instance, electro-static discharge phenomena. In this project, two big semiconductor manufacturers will render available specific test structures, and one important electronic system producer will take part in the application of selected structures and methods from the users' point of view. The study will cover the development of standardized testing methods for the most important VLSI failure mechanisms, namely: latch-up in CMOS, oxide breakdown, hotelectron degradation, electromigration, electro-static-discharge (E.S.D.). Structures proposed to CENELEC TC 117 Standardization Organization by JESSI AC41 will be adopted as a starting point for the first four failure mechanisms. The availability of these structures to the present Consortium at the starting of the project has already been assured.
A well-balanced team of six research institutions will cooperate with semiconductor manufacturers in the development of testing methods and in the design of new test structures. Each institute will take care of the analysis of a specific failure mechanism or testing method. Experience and capability of the selected team covers, beside technical skills, also acquaintance with CECC/CENELEC activity and development of documents meeting the formal requirements of CECC/CENELEC standards. The focus will be on wafer level reliability evaluation with fast methods, while for some mechanisms (E.S.D. in particular), packaged test structures will be used. The effectiveness of the proposed structures will be evaluated also by means of device simulations. Obtained data will be also used to validate extrapolation laws currently employed within IC reliability predictors and simulators. A comparison between experimental data and prediction of circuit reliability simulators will be performed using simple circuits as representative examples. We will also pursue a comparison of the results of wafer level testing with conventional long-term accelerated testing, and, whenever possible, with reliability data concerning finished integrated circuits. The final objective is the proposal to CECC/CENELEC of a new standard, consisting in improved test structures and testing procedures, suitable for a complete reliability evaluation down to a 0.35 um feature size for CMOS technology, including bipolar devices considering a wider range of failure mechanisms. A specific task of the project is devoted to the organization of results and the preparation of documents meeting the formal requirements of CECC/CENELEC standards.

Funding Scheme

CSC - Cost-sharing contracts


Via Gradenigo 6 A
35131 Padova

Participants (8)

70435 Stuttgart
Centre National de la Recherche Scientifique
23,Rue Des Martyrs
38016 Grenoble
Consiglio Nazionale delle Ricerche (CNR)
Via Castagnoli 1
40126 Bologna
Aghia Paraskevi
15310 Athens
National University of Ireland, Cork
Prospect Row
30 Cork
SGS-Thomson Microelectronics
850,Rue Jean Monnet
38926 Crolles
81541 Muenchen
Università degli Studi di Parma
Viale Delle Scienze
43100 Parma