European Exascale Processor Memory Node Design

Project Information

ExaNoDe

Grant agreement ID: 671578

DOI 10.3030/671578

Project closed

EC signature date 29 June 2015

Start date 1 October 2015

End date 30 June 2019

Funded under

• EXCELLENT SCIENCE - Future and Emerging Technologies (FET)

Total cost € 8 629 247,50

EU contribution € 8 629 247,50

Coordinated by

COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
France

CORDIS provides links to public deliverables and publications of HORIZON projects.

Links to deliverables and publications from FP7 projects, as well as links to some specific result types such as dataset and software, are dynamically retrieved from OpenAIRE .

Deliverables

Documents, reports (15)

Report on the ExaNoDe infrastructure requirements
Report and best practices on porting of the mini-applications to the ExaNoDe architecture
Final tuning and evaluation results
Report on the performance bottlenecks of the ExaNoDe architecture
Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Advanced implementation customized for ExaNoDe architecture, interconnect, operating system.
Report on the performance opportunities of the next-generation memory systems
Workshop report
HW-SW integration and tuning
Operating System Support for ExaNoDe [ report and interim prototype]
Report on the performance bottlenecks of the state-of-the-art HPC platforms
Report on the ExaNoDe architecture design guidelines
Design of the ExaNoDe Firmware [ report and initial prototype]

Design of the ExaNoDe Firmware [ report and initial prototype]

Dissemination Strategy Document
Report on the ExaNoDe miniapplications
Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Analysis of the hardware system characteristics and design of a preliminary software implementation.

Demonstrators, pilots, prototypes (2)

Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Final tuned implementation optimized for the delivered prototype machine.
Final report on Firmware and Operating System for ExaNoDe [ report and final prototype]

Other (3)

Final Project Press release
Initial Project Press Release
Project External Website, project flyer and social media presence

Open Research Data Pilot (1)

Data Management Plan for pilot on Open Research Data

Publications

Conference proceedings (21)

The D.A.V.I.D.E. big-data-powered fine-grain power and performance monitoring support

Author(s): Andrea Bartolini, Andrea Borghesi, Antonio Libri, Francesco Beneventi, Daniele Gregori, Simone Tinti, Cosimo Gianfreda, Piero Altoè
Published in: Proceedings of the 15th ACM International Conference on Computing Frontiers - CF '18, 2018, Page(s) 303-308, ISBN 9781-450357616
Publisher: ACM Press
DOI: 10.1145/3203217.3205863

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision

Author(s): Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini
Published in: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, Page(s) 2910-2910, ISBN 978-1-4799-5341-7
Publisher: IEEE
DOI: 10.1109/iscas.2016.7539213

Ultra-low swing CMOS transceiver for 2.5-D integrated systems

Author(s): Przemyslaw Mroszczyk, Vasilis F. Pavlidis
Published in: 2018 19th International Symposium on Quality Electronic Design (ISQED), 2018, Page(s) 262-267, ISBN 978-1-5386-1214-9
Publisher: IEEE
DOI: 10.1109/isqed.2018.8357298

An Efficient Wait-free Resizable Hash Table

Author(s): Panagiota Fatourou, Nikolaos D. Kallimanis, Thomas Ropars
Published in: Proceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures - SPAA '18, 2018, Page(s) 111-120, ISBN 9781-450357999
Publisher: ACM Press
DOI: 10.1145/3210377.3210408

Chipmunk: A systolically scalable 0.9 mm 2 , 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference

Author(s): Francesco Conti, Lukas Cavigelli, Gianna Paulin, Igor Susmelj, Luca Benini
Published in: 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, Page(s) 1-4, ISBN 978-1-5386-2483-8
Publisher: IEEE
DOI: 10.1109/cicc.2018.8357068

Leveraging Data-Flow Task Parallelism for Locality-Aware Dynamic Scheduling on Heterogeneous Platforms

Author(s): Osman Seckin Simsek, Andi Drebes, Antoniu Pop
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 540-549, ISBN 978-1-5386-5555-9
Publisher: IEEE
DOI: 10.1109/ipdpsw.2018.00093

Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Author(s): Przemyslaw Mroszczyk, Vasilis F. Pavlidis
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/iscas.2018.8351057

Automated Analysis of Task-Parallel Execution Behavior Via Artificial Neural Networks

Author(s): Richard Neill, Andi Drebes, Antoniu Pop
Published in: 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2018, Page(s) 647-656, ISBN 978-1-5386-5555-9
Publisher: IEEE
DOI: 10.1109/ipdpsw.2018.00105

Lock Oscillation: Boosting the Performance of Concurrent Data Structures

Author(s): Panagiota Fatourou, and Nikolaos D. Kallimanis
Published in: 21st International Conference on Principles of Distributed Systems (OPODIS 2017), 2017, Page(s) 8:1--8:17, ISBN 978-3-95977-061-3
Publisher: Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik
DOI: 10.4230/lipics.opodis.2017.8

Enabling a reliable STT-MRAM main memory simulation

Author(s): Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojković
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '17, 2017, Page(s) 283-292, ISBN 9781-450353359
Publisher: ACM Press
DOI: 10.1145/3132402.3132416

Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned

Author(s): Milan Radulovic, Kazi Asifuzzaman, Darko Zivanovic, Nikola Rajovic, Guillaume Colin de Verdiere, Dirk Pleiter, Manolis Marazakisl, Nikolaos Kallimanis, Paul Carpenter, Petar Radojkovic, Eduard Ayguade
Published in: 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2018, Page(s) 250-257, ISBN 978-1-5386-7769-8
Publisher: IEEE
DOI: 10.1109/CAHPC.2018.8645891

Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools

Author(s): Beneventi, Francesco; Bartolini, Andrea; Cavazzoni, Carlo; Benini, Luca
Published in: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, Page(s) 1038-1043
Publisher: IEEE
DOI: 10.3929/ethz-b-000192078

User-space APIs for dynamic power management in many-core ARMv8 computing nodes

Author(s): Daniele Bortolotti, Simone Tinti, Piero Altoe, Andrea Bartolini
Published in: 2016 International Conference on High Performance Computing & Simulation (HPCS), 2016, Page(s) 675-681, ISBN 978-1-5090-2088-1
Publisher: IEEE
DOI: 10.1109/HPCSim.2016.7568400

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Author(s): Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoit Dupont de Dinechin
Published in: 2017 Euromicro Conference on Digital System Design (DSD), 2017, Page(s) 486-493, ISBN 978-1-5386-2146-2
Publisher: IEEE
DOI: 10.1109/DSD.2017.37

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Author(s): Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
Published in: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, Page(s) 1-8, ISBN 978-1-5090-6462-5
Publisher: IEEE
DOI: 10.1109/PATMOS.2017.8106979

COUNTDOWN: a Run-time Library for Performance-Neutral Energy Saving in MPI Applications

Author(s): Cesarini, Daniele; Bartolini, Andrea; Bonfà, Pietro; Cavazzoni, Carlo; Benini, Luca
Published in: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2018, ISBN 978-1-4503-6591-8
Publisher: ACM
DOI: 10.3929/ethz-b-000313834

Interactive visualization of cross-layer performance anomalies in dynamic task-parallel applications and systems

Author(s): Andi Drebes, Antoniu Pop, Karine Heydemann, Albert Cohen
Published in: 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2016, Page(s) 274-283, ISBN 978-1-5090-1953-3
Publisher: IEEE
DOI: 10.1109/ISPASS.2016.7482102

Scalable Task Parallelism for NUMA - A Uniform Abstraction for Coordinated Scheduling and Memory Management

Author(s): Andi Drebes, Antoniu Pop, Karine Heydemann, Albert Cohen, Nathalie Drach
Published in: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16, 2016, Page(s) 125-137, ISBN 9781-450341219
Publisher: ACM Press
DOI: 10.1145/2967938.2967946

Language-Centric Performance Analysis of OpenMP Programs with Aftermath

Author(s): Andi Drebes, Jean-Baptiste Bréjon, Antoniu Pop, Karine Heydemann, Albert Cohen
Published in: International Workshop on OpenMP, IWOMP16: OpenMP: Memory, Devices, and Tasks, 2016, Page(s) 237-250
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-45550-1_17

Performance Impact of a Slower Main Memory - A case study of STT-MRAM in HPC

Author(s): Kazi Asifuzzaman, Milan Pavlovic, Milan Radulovic, David Zaragoza, Ohseong Kwon, Kyung-Chang Ryoo, Petar Radojković
Published in: Proceedings of the Second International Symposium on Memory Systems - MEMSYS '16, 2016, Page(s) 40-49, ISBN 9781-450343053
Publisher: ACM Press
DOI: 10.1145/2989081.2989082

Large-Memory Nodes for Energy Efficient High-Performance Computing

Author(s): Darko Zivanovic, Milan Radulovic, Germán Llort, David Zaragoza, Janko Strassburg, Paul M. Carpenter, Petar Radojković, Eduard Ayguadé
Published in: Proceedings of the Second International Symposium on Memory Systems - MEMSYS '16, 2016, Page(s) 3-9, ISBN 9781-450343053
Publisher: ACM Press
DOI: 10.1145/2989081.2989083

Peer reviewed articles (9)

Accelerated Visual Context Classification on a Low-Power Smartwatch

Author(s): Francesco Conti, Daniele Palossi, Renzo Andri, Michele Magno, Luca Benini
Published in: IEEE Transactions on Human-Machine Systems, 2017, Page(s) 1-12, ISSN 2168-2291
Publisher: IEEE Systems, Man, and Cybernetics Society
DOI: 10.1109/thms.2016.2623482

Energy Efficient Flash ADC with PVT Variability Compensation through Advanced Body Biasing

Author(s): Przemyslaw Mroszczyk, John Goodacre, Vasilis F. Pavlidis
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, Page(s) 1-1, ISSN 1549-7747
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcsii.2019.2891580

Fuse

Author(s): Richard Neill, Andi Drebes, Antoniu Pop
Published in: ACM Transactions on Architecture and Code Optimization, Issue 14/4, 2017, Page(s) 1-26, ISSN 1544-3566
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3148054

Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip

Author(s): Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue 35/4, 2016, Page(s) 623-636, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tcad.2015.2474382

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Author(s): Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, Issue 64/9, 2017, Page(s) 2481-2494, ISSN 1549-8328
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCSI.2017.2698019

Self-Aware Thermal Management for High-Performance Computing Processors

Author(s): Andrea Bartolini, Roberto Diversi, Daniele Cesarini, Francesco Beneventi
Published in: IEEE Design & Test, Issue 35/5, 2018, Page(s) 28-35, ISSN 2168-2356
Publisher: IEEE Computer Society
DOI: 10.1109/MDAT.2017.2774774

PROFET: modeling system performance and energy without simulating the CPU

Author(s): Milan Radulovic, Rommel Sanchez Verdejo, Paul Carpenter, Petar Radojković, Bruce Jacob, Eduard Ayguadé
Published in: Proceedings of the ACM on Measurement and Analysis of Computing Systems, Issue Volume 3 Issue 2, 2019, ISSN 2476-1249
Publisher: ACM

JSCs Horizon 2020

Author(s): Pleiter, Dirk
Published in: Innovatives Supercomputing in Deutschland 13(2), 64(2015)., Issue 6, 2015, ISSN 0302-9743
Publisher: Springer Verlag

Main Memory in HPC

Author(s): Darko Zivanovic, Milan Pavlovic, Milan Radulovic, Hyunsung Shin, Jongpil Son, Sally A. Mckee, Paul M. Carpenter, Petar Radojković, Eduard Ayguadé
Published in: ACM Transactions on Architecture and Code Optimization, Issue 14/1, 2017, Page(s) 1-26, ISSN 1544-3566
Publisher: Association for Computing Machinary, Inc.
DOI: 10.1145/3023362

Book chapters (1)

HPC Benchmarking: Scaling Right and Looking Beyond the Average

Author(s): Milan Radulovic, Kazi Asifuzzaman, Paul Carpenter, Petar Radojković, Eduard Ayguadé
Published in: Euro-Par 2018: Parallel Processing - 24th International Conference on Parallel and Distributed Computing, Turin, Italy, August 27 - 31, 2018, Proceedings, Issue 11014, 2018, Page(s) 135-146, ISBN 978-3-319-96982-4
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-96983-1_10

Thesis and dissertations (1)

Memory systems for high-performance computing: the capacity and reliability implications

Author(s): Živanovič, Darko
Published in: Tesis Doctorals en Xarxa, 2018
Publisher: Universitat Politècnica de Catalunya