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Open transPREcision COMPuting

Deliverables

Second summer school

Second summer school organized.

Third summer school

Third summer school organized.

First summer school

First summer school organized.

Set up of intranet, data repository, and project management tool

OPRECOMP will make use of a web-based professional project management tool in order to facilitate the better management of all administrative, technical, and financial activities of the project.

Web-site and project logo

OPRECOMP public web-site and content, logo, presentation templates, and material for the identity of the project.

Final data management plan

The data management plan initially released on month M06 will be updated and finalized.

Initial data management plan

A first version of the data management plan will be released.

Final report of big data applications using transprecision computing

Final report on the Big Data application in T8.3 using the kW platform.

ReRAM and heterogeneous 3D-memory architecture models

The outputs of this deliverable are ReRAM and heterogeneous 3D-Memory models, which allow on different abstraction levels (from circuit to system level) explorations of appropriate memory architectures.

Summer of code report

Report on the 2-year summer of code activity outcome.

Initial report of embedded deep learning using transprecision computing

Report detailing the initial gains obtained by employing transprecision computing in deep learning applications

Evaluation results for heterogeneous memories

Report on the energy efficiency of heterogeneous memory hierarchies based on emerging memory technologies.

Final communication activity and plan report

A report on planned/completed communication activities will be provided.

Final report on micro-benchmarks

Final report on the applications and micro-benchmarks selected for the project as well as the measured performance on state-of-the-art architectures.

Simulation results for NEMS memory devices

Evaluation results of non-conventional NEMS memory devices will be provided by UNIPG.

Stochastic logic gate modeling

Report describing the functioning model of stochastic logic gates to be operated under large fluctuations.

Fundamental physics limits

Report that formalizes the fundamental physics limits of computation for logic gates and memory devices.

Final report of embedded deep learning using transprecision computing

Report detailing all the gains obtained by employing transprecision computing in deep learning applications

Initial report of big data applications using transprecision computing

Initial report on the Big Data application in T8.3 using the kW platform.

Evaluation of approximate computing techniques

The output of this deliverable is a quantification of the benefits of memorization, task elimination, loop perforation, randomized sparsification and sketching, and skipping memory accesses.

Report on applications and micro-benchmarks performance demo

Report on the achieved performance of the selected applications and micro-benchmarks by using the full transprecision framework developed during the project.

Final version of the algorithms

Report on the achieved gains attained with the new algorithms for data assimilation, linear algebra, graph analytics and the approximate computing.

Initial dissemination and exploitation plan report

Initial report on dissemination and exploitation. The report will include also a market analysis for the technology developed by OPRECOMP.

Processing unit for controllable precision

Specification of the processing unit with precision control that will be used in mW and kW range systems.

Intermediate applications progress report

Report describing all the progress made on all micro-benchmarks.

Definition of the hardware abstraction layer

Definition of the hardware abstraction layer that controls various precision configuration options of architectures.

Final report on scientific computation using transprecision computing

Report on scientific computation kernels running on the kW platform.

Error-energy relations: fundamental limits

Report containing the analysis of the relation between minimum energy required for logic operation that depends on fundamental physical constrains.

Initial communication activity and plan report

A report on planned/completed communication activities will be provided.

Transprecision software stack design

An initial characterization of relevant applications and/or proxy benchmarks for these applications. The deliverable will present the initial design and elaboration of functionality of the software stack.

Numerical analysis of algorithms

Report that assesses the effect of transprecision computing on the algorithms.

Initial report on scientific computation using transprecision computing

Initial report on scientific computation kernels running on the kW platform.

Intermediate dissemination and exploitation plan report

Intermediate report on dissemination and exploitation. The report will include also a market analysis for the technology developed by OPRECOMP.

Prototype version of the algorithms

A report describing the advances attained with the algorithms during the initial refactoring phase.

Intermediate communication activity and plan report

A report on planned/completed communication activities will be provided.

Error-energy relations: technological limits

Report containing the analysis of the relation between minimum energy required for logic operation and result accuracy bounded by limits imposed by technology selected in WP4.

Numerical analysis of transprecision

Report that formalizes the extension of fundamental principles of numerical analysis to variable precision arithmetic.

Final dissemination and exploitation plan report

Final report on dissemination and exploitation. The report will include also a market analysis for the technology developed by OPRECOMP.

NEMS/MEMS demo report

Report on the experimental verification of technology limits.

Final applications progress report

Report describing all the progress made on all micro-benchmarks.

Evaluation of transprecision

The output of this deliverable is a quantification of the benefits of transprecision (e.g., low precision floating-point vs fixed-point representation) and stochastic estimators on the five problem domains.

Error resilience

Report with a precise characterization of the algorithmic kernels to be targeted by the approximate computing techniques on the five problem domains.

Quality metrics

A concise definition of metrics to be used in the quality assessment of the solutions produced by the algorithms.

Initial report on micro-benchmarks

Initial report on the applications and micro-benchmarks selected for the project as well as the measured performance on state-of-the-art architectures.

Initial applications progress report

Report describing all the progress made on all micro-benchmarks.

Initial version of the kW pilot-platform

Initial working version of the HPC node. It will be used in WP8 to demonstrate the kW range apps.

Final version of the kW pilot-platform

Final working version of the HPC node. It will be used in WP8 to demonstrate the kW range apps.

Final version of the mW pilot-platform

Final working version of the mW platform. It will be used in WP8 to demonstrate the mW range apps.

Initial version of the mW pilot-platform

Initial working version of the mW platform. It will be used in WP8 to demonstrate the mW range apps.

Intermediate version of transprecision software stack

The initial version of the software stack will be early available for applications (WP7) and initial demonstrations (WP8). The final version will be used to make the final evaluations of the systems in the mW and kW range.

Initial version of transprecision software stack

The initial version of the software stack will be early available for applications (WP7) and initial demonstrations (WP8). The final version will be used to make the final evaluations of the systems in the mW and kW range.

Final version of transprecision software stack

The initial version of the software stack will be early available for applications (WP7) and initial demonstrations (WP8). The final version will be used to make the final evaluations of the systems in the mW and kW range.

Publications

NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations

Author(s): Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Sander Stuijk, Henk Corporaal
Published in: 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019, Page(s) 263-269, ISBN 978-1-7281-4884-7
Publisher: IEEE
DOI: 10.1109/fpl.2019.00050

XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs

Author(s): Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gurkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini
Published in: 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2020, Page(s) 1-3, ISBN 978-1-7281-6347-5
Publisher: IEEE
DOI: 10.1109/coolchips49199.2020.9097644

Prediction of Time-to-Solution in Material Science Simulations Using Deep Learning

Author(s): Federico Pittino, Pietro Bonfà, Andrea Bartolini, Fabio Affinito, Luca Benini, Carlo Cavazzoni
Published in: Proceedings of the Platform for Advanced Scientific Computing Conference, 2019, Page(s) 1-9, ISBN 9781450367707
Publisher: ACM
DOI: 10.1145/3324989.3325720

Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack

Author(s): Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner
Published in: International Conference on Field Programmable Logic and Applications, 2020, ISBN 978-1-7281-9902-3
Publisher: IEEE
DOI: 10.1109/fpl50879.2020.00058

HaRMony - Heterogeneous-Reliability Memory and QoS-Aware Energy Management on Virtualized Servers

Author(s): Konstantinos Tovletoglou, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, 2020, Page(s) 575-590, ISBN 9781450371025
Publisher: ACM
DOI: 10.1145/3373376.3378489

HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments

Author(s): Dionysios Diamantopoulos, Christoph Hagleitner
Published in: 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019, Page(s) 71-74, ISBN 978-1-7281-1601-3
Publisher: IEEE
DOI: 10.1109/asap.2019.00-27

Combining learning and optimization for transprecision computing

Author(s): Andrea Borghesi, Giuseppe Tagliavini, Michele Lombardi, Luca Benini, Michela Milano
Published in: Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020, Page(s) 10-18, ISBN 9781450379564
Publisher: ACM
DOI: 10.1145/3387902.3392615

A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference

Author(s): Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti; Luca Benini; Davide Rossi
Published in: IEEE Computer Society Annual Symposium on VLSI, 2020, ISBN 978-1-7281-5775-7
Publisher: IEEE
DOI: 10.1109/isvlsi49217.2020.000-5

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

Author(s): Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gomez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal
Published in: 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, Page(s) 9-17, ISBN 978-1-7281-9902-3
Publisher: IEEE
DOI: 10.1109/fpl50879.2020.00014

Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead

Author(s): Eder F. Zulian, Christian Weis, Norbert Wehn
Published in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, Page(s) 1-5, ISBN 978-1-7281-3320-1
Publisher: IEEE
DOI: 10.1109/iscas45731.2020.9180873

DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes - work-in-progress

Author(s): Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
Published in: Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019, Page(s) 1-2, ISBN 9781450369237
Publisher: ACM
DOI: 10.1145/3349567.3351726

Precision variable anonymization method supporting transprecision computing

Author(s): Keiya Harada, Henri-Pierre Charles, Hiroaki Nishi
Published in: 2020 22nd International Conference on Advanced Communication Technology (ICACT), 2020, Page(s) 35-42, ISBN 979-11-88428-04-5
Publisher: IEEE
DOI: 10.23919/icact48636.2020.9061512

CBinfer - Change-Based Inference for Convolutional Neural Networks on Video Data

Author(s): Lukas Cavigelli, Philippe Degen, Luca Benini
Published in: Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017, Page(s) 1-8, ISBN 9781450354875
Publisher: ACM
DOI: 10.1145/3131885.3131906

Mixed-data-model heterogeneous compilation and OpenMP offloading

Author(s): Andreas Kurth, Koen Wolters, Björn Forsberg, Alessandro Capotondi, Andrea Marongiu, Tobias Grosser, Luca Benini
Published in: Proceedings of the 29th International Conference on Compiler Construction, 2020, Page(s) 119-131, ISBN 9781450371209
Publisher: ACM
DOI: 10.1145/3377555.3377891

Fast validation of DRAM protocols with timed petri nets

Author(s): Matthias Jung, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems, 2019, Page(s) 133-147, ISBN 9781450372060
Publisher: ACM
DOI: 10.1145/3357526.3357556

Extended Bit-Plane Compression for Convolutional Neural Network Accelerators

Author(s): Lukas Cavigelli, Luca Benini
Published in: 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2019, Page(s) 279-283, ISBN 978-1-5386-7884-8
Publisher: IEEE
DOI: 10.1109/aicas.2019.8771562

Network-accelerated non-contiguous memory transfers

Author(s): Salvatore Di Girolamo, Konstantin Taranov, Andreas Kurth, Michael Schaffner, Timo Schneider, Jakub Beránek, Maciej Besta, Luca Benini, Duncan Roweth, Torsten Hoefler
Published in: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2019, Page(s) 1-14, ISBN 9781450362290
Publisher: ACM
DOI: 10.1145/3295500.3356189

Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX

Author(s): Pasquale Davide Schiavone, Davide Rossi, Antonio Pullini, Alfio Di Mauro, Francesco Conti, Luca Benini
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, Page(s) 1-3, ISBN 978-1-5386-7627-1
Publisher: IEEE
DOI: 10.1109/s3s.2018.8640145

DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms

Author(s): Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2020, Page(s) 298-312, ISBN 978-1-7281-7383-2
Publisher: IEEE
DOI: 10.1109/micro50266.2020.00035

PHRYCTORIA: A Messaging System for Transprecision OpenCAPI-attached FPGA Accelerators.

Author(s): Dionysios Diamantopoulos; Mitra Purandare; Burkhard Ringlein; Christoph Hagleitner
Published in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020
Publisher: IEEE
DOI: 10.1109/ipdpsw50202.2020.00023

Integrating DRAM power-down modes in gem5 and quantifying their impact

Author(s): Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '17, 2017, Page(s) 86-95, ISBN 9781-450353359
Publisher: ACM Press
DOI: 10.1145/3132402.3132444

Using run-time reverse-engineering to optimize DRAM refresh

Author(s): Deepak M. Mathew, Éder F. Zulian, Matthias Jung, Kira Kraft, Christian Weis, Bruce Jacob, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '17, 2017, Page(s) 115-124, ISBN 9781-450353359
Publisher: ACM Press
DOI: 10.1145/3132402.3132419

Balanced CSR Sparse Matrix-Vector Product on Graphics Processors

Author(s): Goran Flegar, Enrique S. Quintana-Ortí
Published in: Euro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 – September 1, 2017, Proceedings, 2017, Page(s) 697-709
Publisher: Springer International Publishing
DOI: 10.1007/978-3-319-64203-1_50

Impact of temporal subsampling on accuracy and performance in practical video classification

Author(s): F. Scheidegger, L. Cavigelli, M. Schaffner, A. C. I. Malossi, C. Bekas, L. Benini
Published in: 2017 25th European Signal Processing Conference (EUSIPCO), 2017, Page(s) 996-1000, ISBN 978-0-9928626-7-1
Publisher: IEEE
DOI: 10.23919/EUSIPCO.2017.8081357

Variable-Size Batched LU for Small Matrices and Its Integration into Block-Jacobi Preconditioning

Author(s): Hartwig Anzt, Jack Dongarra, Goran Flegar, Enrique S. Quintana-Orti
Published in: 2017 46th International Conference on Parallel Processing (ICPP), 2017, Page(s) 91-100, ISBN 978-1-5386-1042-8
Publisher: IEEE
DOI: 10.1109/ICPP.2017.18

Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis

Author(s): Lei Li, Michael Gautschi, Luca Benini
Published in: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017), Thessaloniki, Greece, September 25-27, 2017, 2017, Page(s) 1-8, ISBN 978-1-5090-6462-5
Publisher: IEEE
DOI: 10.1109/PATMOS.2017.8106987

A sub-10mW real-time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC

Author(s): Simone Benatti, Giovanni Rovere, Jonathan Bosser, Fabio Montagna, Elisabetta Farella, Horian Glaser, Philipp Schonle, Thomas Burger, Schekeb Fateh, Qiuting Huang, Luca Benini
Published in: 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 2017, Page(s) 139-144, ISBN 978-1-5090-6707-7
Publisher: IEEE
DOI: 10.1109/IWASI.2017.7974234

Work-in-Progress: Quantized NNs as the Definitive Solution for Inference on Low-Power ARM MCUs?

Author(s): Manuele Rusci, Alessandro Capotondi, Francesco Conti, Luca Benini
Published in: 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), November 2018, 2018, Page(s) 1-2, ISBN 978-1-5386-5562-7
Publisher: IEEE
DOI: 10.1109/CODESISSS.2018.8525915

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing

Author(s): Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/ISCAS.2018.8351816

The transprecision computing paradigm: Concept, design, and applications

Author(s): A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew Emerson, Andres Tomas, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1105-1110, ISBN 978-3-9819263-0-9
Publisher: IEEE
DOI: 10.23919/DATE.2018.8342176

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?

Author(s): Manuele Rusci, Lukas Cavigelli, Luca Benini
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/ISCAS.2018.8351807

A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics

Author(s): Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/ISCAS.2018.8351749

A transprecision floating-point platform for ultra-low power computing

Author(s): Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benin
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1051-1056, ISBN 978-3-9819263-0-9
Publisher: IEEE
DOI: 10.23919/date.2018.8342167

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

Author(s): Andreas Kurth, Pirmin Vogel, Andrea Marongiu, Luca Benini
Published in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, Page(s) 292-300, ISBN 978-1-5386-8477-1
Publisher: IEEE
DOI: 10.1109/iccd.2018.00052

An Energy-Efficient IoT node for HMI applications based on an ultra-low power Multicore Processor

Author(s): Victor Kartsch, Marco Guermandi, Simone Benatti, Fabio Montagna, Luca Benini
Published in: 2019 IEEE Sensors Applications Symposium (SAS), 2019, Page(s) 1-6, ISBN 978-1-5386-7713-1
Publisher: IEEE
DOI: 10.1109/SAS.2019.8705984

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

Author(s): Di Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, Luca; id_orcid0000-0001-8068-3806
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 1, 2018
Publisher: IEEE
DOI: 10.3929/ethz-b-000314386

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI

Author(s): Fabian Schuiki, Michael Schaffner, Luca Benini
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 662-667, ISBN 978-3-9819263-2-3
Publisher: IEEE
DOI: 10.23919/DATE.2019.8715007

Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA

Author(s): Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 654-657, ISBN 978-3-9819263-2-3
Publisher: IEEE
DOI: 10.23919/DATE.2019.8714897

Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX

Author(s): Schiavone, Pasquale D.; Rossi, Davide; Pullini, Antonio; Di Mauro, Alfio; Conti, Francesco; id_orcid0000-0002-7924-933X; Benini, Luca
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 1, 2018
Publisher: IEEE
DOI: 10.3929/ethz-b-000314427

High-Performance GPU Implementation of PageRank with Reduced Precision Based on Mantissa Segmentation

Author(s): Thomas Grutzmacher, Hartwig Anzt, Florian Scheidegger, Enrique S. Quintana-Orti
Published in: 2018 IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3), 2018, Page(s) 61-68, ISBN 978-1-7281-0186-6
Publisher: IEEE
DOI: 10.1109/IA3.2018.00015

HelmGemm: Managing GPUs and FPGAs for transprecision GEMM workloads in containerized environments

Author(s): Dionysios Diamantopoulos, Christoph Hagleitner
Published in: 2019
Publisher: Cornell University

An In-DRAM Neural Network Processing Engine

Author(s): Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5, ISBN 978-1-7281-0397-6
Publisher: IEEE
DOI: 10.1109/iscas.2019.8702458

Coherently Attached Programmable Near-Memory Acceleration Platform and its application to Stencil Processing

Author(s): Jan van Lunteren, Ronald Luijten, Dionysios Diamantopoulos, Florian Auernhammer, Christoph Hagleitner, Lorenzo Chelini, Stefano Corda, Gagandeep Singh
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 668-673, ISBN 978-3-9819263-2-3
Publisher: IEEE
DOI: 10.23919/date.2019.8715088

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 698-703, ISBN 978-3-9819263-2-3
Publisher: IEEE
DOI: 10.23919/date.2019.8714942

A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping

Author(s): Dionysios Diamantopoulos, Christoph Hagleitner
Published in: 2018 International Conference on Field-Programmable Technology (FPT), 2018, Page(s) 338-341, ISBN 978-1-7281-0214-6
Publisher: IEEE
DOI: 10.1109/fpt.2018.00068

Efficient coding scheme for DDR4 memory subsystems

Author(s): Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn, Florian Longnos
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '18, 2018, Page(s) 148-157, ISBN 9781-450364751
Publisher: ACM Press
DOI: 10.1145/3240302.3240424

Driving into the memory wall - the role of memory for advanced driver assistance systems and autonomous driving

Author(s): Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '18, 2018, Page(s) 377-386, ISBN 9781-450364751
Publisher: ACM Press
DOI: 10.1145/3240302.3240322

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment - Case Study on a Floating-Point Unit

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: Proceedings of the International Symposium on Low Power Electronics and Design - ISLPED '18, 2018, Page(s) 1-6, ISBN 9781-450357043
Publisher: ACM Press
DOI: 10.1145/3218603.3218617

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Page(s) 171-176, ISBN 978-1-5386-5992-2
Publisher: IEEE
DOI: 10.1109/iolts.2018.8474084

The Role of Memories in Transprecision Computing

Author(s): Christian Weis, Matthias Jung, Eder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/iscas.2018.8351768

ecTALK: Energy efficient coherent transprecision accelerators — The bidirectional long short-term memory neural network case

Author(s): Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner
Published in: 2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2018, Page(s) 1-3, ISBN 978-1-5386-6103-1
Publisher: IEEE
DOI: 10.1109/coolchips.2018.8373077

Fast Blocking of Householder Reflectors on Graphics Processors

Author(s): Andres E. Tomas Dominguez, Enrique S. Quintana Orti
Published in: 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), 2018, Page(s) 385-393, ISBN 978-1-5386-4975-6
Publisher: IEEE
DOI: 10.1109/pdp2018.2018.00068

Extending the POWER Architecture with Transprecision Co-Processors

Author(s): Heiner Giefers, Dionysios Diamantopoulos
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5, ISBN 978-1-5386-4881-0
Publisher: IEEE
DOI: 10.1109/iscas.2018.8351755

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs

Author(s): Deepak M. Mathew, Martin Schultheis, Carl C. Rheinlander, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 293-296, ISBN 978-3-9819263-0-9
Publisher: IEEE
DOI: 10.23919/date.2018.8342023

Improving the error behavior of DRAM by exploiting its Z-channel property

Author(s): Kira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1492-1495, ISBN 978-3-9819263-0-9
Publisher: IEEE
DOI: 10.23919/date.2018.8342249

Reduction to Band Form for the Singular Value Decomposition on Graphics Accelerators

Author(s): Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Enrique S. Quintana-Ortí
Published in: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM'18, 2018, Page(s) 51-60, ISBN 9781-450356459
Publisher: ACM Press
DOI: 10.1145/3178442.3178448

An Open Source and Open Hardware Deep Learning-Powered Visual Navigation Engine for Autonomous Nano-UAVs

Author(s): Daniele Palossi, Francesco Conti, Luca Benini
Published in: 2019 15th International Conference on Distributed Computing in Sensor Systems (DCOSS), 2019, Page(s) 604-611, ISBN 978-1-7281-0570-3
Publisher: IEEE
DOI: 10.1109/dcoss.2019.00111

Graptor - efficient pull and push style vectorized graph processing

Author(s): Hans Vandierendonck
Published in: Proceedings of the 34th ACM International Conference on Supercomputing, 2020, Page(s) 1-13, ISBN 9781450379830
Publisher: ACM
DOI: 10.1145/3392717.3392753

System simulation with PULP virtual platform and SystemC

Author(s): Éder F. Zulian, Germain Haugou, Christian Weis, Matthias Jung, Norbert Wehn
Published in: Proceedings of the Conference on Rapid Simulation and Performance Evaluation: Methods and Tools, 2020, Page(s) 1-7, ISBN 9781450377775
Publisher: ACM
DOI: 10.1145/3375246.3375256

Half-Precision Floating-Point Formats for PageRank: Opportunities and Challenges

Author(s): Amir Sabbagh Molahosseini, Hans Vandierendonck
Published in: 2020 IEEE High Performance Extreme Computing Conference (HPEC), 2020, Page(s) 1-7, ISBN 978-1-7281-9219-2
Publisher: IEEE
DOI: 10.1109/hpec43674.2020.9286179

CAS-CNN: A deep convolutional neural network for image compression artifact suppression

Author(s): Lukas Cavigelli; Pascal Hager; Luca Benini
Published in: International Joint Conference on Neural Networks (IJCNN), 2017
Publisher: IEEE
DOI: 10.1109/ijcnn.2017.7965927

DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search

Author(s): I. Tsiokanos, L. Mukhanov, G. Georgakoudis, D. S. Nikolopoulos , G. Karakonstantis
Published in: Design, Automation and Test in Europe Conference and Exhibition, 2020
Publisher: IEEE
DOI: 10.23919/date48585.2020.9116363

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Author(s): Andreas Kurth, Pirmin Vogel, Alessandro Capotondi, Andrea Marongiu, Luca Benini
Published in: Proceedings of Computer Architecture Research with RISC-V Workshop, 2017
Publisher: ETHz
DOI: 10.3929/ethz-b-000219249

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

Author(s): Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018, Page(s) 1-3, ISBN 978-1-5386-7627-1
Publisher: IEEE
DOI: 10.1109/s3s.2018.8640136

Temporal Variability Analysis in sEMG Hand Grasp Recognition using Temporal Convolutional Networks

Author(s): Marcello Zanghieri; Simone Benatti; Francesco Conti; Alessio Burrello; Luca Benini
Published in: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, ISBN 978-1-7281-4922-6
Publisher: IEEE
DOI: 10.1109/aicas48895.2020.9073888

ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor

Author(s): Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini
Published in: 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, Page(s) 1-6, ISBN 978-1-7281-1085-1
Publisher: IEEE
DOI: 10.1109/dac18072.2020.9218661

Constrained deep neural network architecture search for IoT devices accounting for hardware calibration

Author(s): Florian Scheidegger, Luca Benini, Costas Bekas, Cristiano Malossi
Published in: 2019
Publisher: Curran
DOI: 10.13039/501100000780

AIR: Iterative refinement acceleration using arbitrary dynamic precision

Author(s): JunKyu Lee, Gregory D. Peterson, Dimitrios S. Nikolopoulos, Hans Vandierendonck
Published in: Parallel Computing, 97, 2020, Page(s) 102663, ISSN 0167-8191
Publisher: Elsevier BV
DOI: 10.1016/j.parco.2020.102663

ExHero: Execution History-aware Error-rate Estimation in Pipelined Designs

Author(s): Ioannis Tsiokanos, Georgios Karakonstantis
Published in: IEEE Micro, 2020, Page(s) 1-1, ISSN 0272-1732
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/mm.2020.3012045

Efficient Hardware Architectures for 1D- and MD-LSTM Networks

Author(s): Vladimir Rybalkin, Chirag Sudarshan, Christian Weis, Jan Lappas, Norbert Wehn , Li Cheng
Published in: Journal of Signal Processing Systems, 2020, ISSN 0920-8542
Publisher: Kluwer Academic Publishers
DOI: 10.1007/s11265-020-01554-x

Thermodynamic reversible transformations in micro-electro-mechanical systems

Author(s): Igor Neri, Miquel López-Suárez
Published in: The European Physical Journal B, 91/6, 2018, ISSN 1434-6028
Publisher: Springer Verlag
DOI: 10.1140/epjb/e2018-80632-9

Fundamental Limits in Dissipative Processes during Computation

Author(s): Davide Chiucchiú, Maria Cristina Diamantini, Miquel López-Suárez, Igor Neri, Luca Gammaitoni
Published in: Entropy, 21/9, 2019, Page(s) 822, ISSN 1099-4300
Publisher: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/e21090822

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Author(s): Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, 64/9, 2017, Page(s) 2481-2494, ISSN 1549-8328
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCSI.2017.2698019

Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection

Author(s): Fabio Montagna, Simone Benatti, Davide Rossi
Published in: Journal of Low Power Electronics and Applications, 7/2, 2017, Page(s) 16, ISSN 2079-9268
Publisher: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/jlpea7020016

A machine learning approach for automated wide-range frequency tagging analysis in embedded neuromonitoring systems

Author(s): Fabio Montagna, Marco Buiatti, Simone Benatti, Davide Rossi, Elisabetta Farella, Luca Benini
Published in: Methods, 129, 2017, Page(s) 96-107, ISSN 1046-2023
Publisher: Academic Press
DOI: 10.1016/j.ymeth.2017.06.019

A Prosthetic Hand Body Area Controller Based on Efficient Pattern Recognition Control Strategies

Author(s): Simone Benatti, Bojan Milosevic, Elisabetta Farella, Emanuele Gruppioni, Luca Benini
Published in: Sensors, 17/4, 2017, Page(s) 869, ISSN 1424-8220
Publisher: Multidisciplinary Digital Publishing Institute (MDPI)
DOI: 10.3390/s17040869

"A 2.2-<inline-formula> <tex-math notation=""LaTeX"">$\mu$ </tex-math> </inline-formula>W Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes"

Author(s): Giovanni Rovere, Schekeb Fateh, Luca Benini
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8/3, 2018, Page(s) 543-554, ISSN 2156-3357
Publisher: IEEE Circuits and Systems Society
DOI: 10.1109/JETCAS.2018.2828505

Look-ahead in the two-sided reduction to compact band forms for symmetric eigenvalue problems and the SVD

Author(s): Rafael Rodríguez-Sánchez, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Andrés E. Tomás
Published in: Numerical Algorithms, 80/2, 2019, Page(s) 635-660, ISSN 1017-1398
Publisher: Baltzer Science Publishers B.V.
DOI: 10.1007/s11075-018-0500-8

FlexFloat: A Software Library for Transprecision Computing

Author(s): Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018, 2018, Page(s) 1-1, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2018.2883902

NEURA ghe

Author(s): Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
Published in: ACM Transactions on Reconfigurable Technology and Systems, 11/3, 2018, Page(s) 1-24, ISSN 1936-7406
Publisher: Association for Computing Machinery (ACM)
DOI: 10.1145/3284357

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing

Author(s): Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, Page(s) 1-1, ISSN 0278-0070
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TCAD.2018.2834397

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Author(s): Fabian Schuiki, Michael Schaffner, Frank K. Gurkaynak, Luca Benini
Published in: IEEE Transactions on Computers, 68/4, 2019, Page(s) 484-497, ISSN 0018-9340
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tc.2018.2876312

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores

Author(s): Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
Published in: IEEE Transactions on Multi-Scale Computing Systems, 4/2, 2018, Page(s) 99-112, ISSN 2332-7766
Publisher: IEEE
DOI: 10.1109/TMSCS.2017.2769046

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters

Author(s): Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini
Published in: IEEE Embedded Systems Letters, 9/4, 2017, Page(s) 125-128, ISSN 1943-0663
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/LES.2017.2707978

A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems

Author(s): Victor Javier Kartsch, Simone Benatti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
Published in: Information Fusion, 43, 2018, Page(s) 66-76, ISSN 1566-2535
Publisher: Elsevier BV
DOI: 10.1016/j.inffus.2017.11.005

Cost of remembering a bit of information

Author(s): D. Chiuchiù, M. López-Suárez, I. Neri, M. C. Diamantini, L. Gammaitoni
Published in: Physical Review A, 97/5, 2018, Page(s) Phys. Rev. A 97, 052108, ISSN 2469-9926
Publisher: American Physical Society
DOI: 10.1103/PhysRevA.97.052108

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes

Author(s): Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
Published in: IEEE Transactions on Parallel and Distributed Systems, 29/2, 2018, Page(s) 420-434, ISSN 1045-9219
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/TPDS.2017.2752706

Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine

Author(s): Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 9/2, 2019, Page(s) 309-322, ISSN 2156-3357
Publisher: IEEE Circuits and Systems Society
DOI: 10.1109/JETCAS.2019.2905654

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing

Author(s): Simone Benatti, Fabio Montagna, Victor Kartsch, Abbas Rahimi, Davide Rossi, Luca Benini
Published in: IEEE Transactions on Biomedical Circuits and Systems, 13/3, 2019, Page(s) 516-528, ISSN 1932-4545
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tbcas.2019.2914476

Toward a modular precision ecosystem for high-performance computing

Author(s): Hartwig Anzt, Goran Flegar, Thomas Grützmacher, Enrique S Quintana-Ortí
Published in: The International Journal of High Performance Computing Applications, 2019, Page(s) 109434201984654, ISSN 1094-3420
Publisher: SAGE Publications
DOI: 10.1177/1094342019846547

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

Author(s): Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
Published in: IEEE Journal of Solid-State Circuits, 54/7, 2019, Page(s) 1970-1981, ISSN 0018-9200
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/jssc.2019.2912307

Significance-Driven Data Truncation for Preventing Timing Failures

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: IEEE Transactions on Device and Materials Reliability, 19/1, 2019, Page(s) 25-36, ISSN 1530-4388
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/tdmr.2019.2898949

Dynamic look-ahead in the reduction to band form for the singular value decomposition

Author(s): Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Rocío Carratalá-Sáez, Enrique S. Quintana-Ortí
Published in: Parallel Computing, 81, 2019, Page(s) 22-31, ISSN 0167-8191
Publisher: Elsevier BV
DOI: 10.1016/j.parco.2018.11.001

Adaptive precision in block-Jacobi preconditioning for iterative sparse linear system solvers

Author(s): Hartwig Anzt, Jack Dongarra, Goran Flegar, Nicholas J. Higham, Enrique S. Quintana-Ortí
Published in: Concurrency and Computation: Practice and Experience, 31/6, 2019, Page(s) e4460, ISSN 1532-0626
Publisher: John Wiley & Sons Inc.
DOI: 10.1002/cpe.4460

Variable-size batched Gauss–Jordan elimination for block-Jacobi preconditioning on graphics processors

Author(s): Hartwig Anzt, Jack Dongarra, Goran Flegar, Enrique S. Quintana-Ortí
Published in: Parallel Computing, 81, 2019, Page(s) 131-146, ISSN 0167-8191
Publisher: Elsevier BV
DOI: 10.1016/j.parco.2017.12.006

Energy-Efficient Iterative Refinement Using Dynamic Precision

Author(s): JunKyu Lee, Hans Vandierendonck, Mahwish Arif, Gregory D. Peterson, Dimitrios S. Nikolopoulos
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8/4, 2018, Page(s) 722-735, ISSN 2156-3357
Publisher: IEEE Circuits and Systems Society
DOI: 10.1109/jetcas.2018.2850665

Tall-and-skinny QR factorization with approximate Householder reflectors on graphics processors

Author(s): Andrés E. Tomás, Enrique S. Quintana-Ortí
Published in: The Journal of Supercomputing, 76/11, 2020, Page(s) 8771-8786, ISSN 0920-8542
Publisher: Kluwer Academic Publishers
DOI: 10.1007/s11227-020-03176-3

FloatX: A C++ Library for Customized Floating-Point Arithmetic

Author(s): Goran Flegar; Florian Scheidegger; Vedran Novakovic; Giovani Mariani; A. E. Tomás; A. Cristiano M. Malossi, Enrique S. Quintana-Orti
Published in: ACM Trans. Mathematica Software, 2019, ISSN 0272-1732
Publisher: Institute of Electrical and Electronics Engineers
DOI: 10.1109/vlsi-soc.2019.8920307

Thermodynamic reversible transformations in micro-electro- mechanical systems

Author(s): Igor Neri, Miquel Lopez-Suarez
Published in: The European Physical Journal B volume, 2018, ISSN 0920-8542
Publisher: Kluwer Academic Publishers
DOI: 10.1140/epjb/e2018-80632-9

Injective Domain Knowledge in Neural Networks for Transprecision Computing

Author(s): Andrea Borghesi, Federico Baldo, Michele Lombardi, Michela Milano
Published in: Machine Learning, Optimization, and Data Science - 6th International Conference, LOD 2020, Siena, Italy, July 19–23, 2020, Revised Selected Papers, Part I, 12565, 2020, Page(s) 587-600, ISBN 978-3-030-64582-3
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-64583-0_52

Cholesky and Gram-Schmidt Orthogonalization for Tall-and-Skinny QR Factorizations on Graphics Processors

Author(s): Andrés E. Tomás, Enrique S. Quintana-Ortí
Published in: Euro-Par 2019: Parallel Processing - 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings, 11725, 2019, Page(s) 469-480, ISBN 978-3-030-29399-4
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-29400-7_33

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Author(s): Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, 11733, 2019, Page(s) 34-47, ISBN 978-3-030-27561-7
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-27562-4_3

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

Author(s): Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, 11733, 2019, Page(s) 429-441, ISBN 978-3-030-27561-7
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-27562-4_31

Residual Replacement in Mixed-Precision Iterative Refinement for Sparse Linear Systems

Author(s): Hartwig Anzt, Goran Flegar, Vedran Novaković, Enrique S. Quintana-Ortí, Andrés E. Tomás
Published in: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, 11203, 2018, Page(s) 554-561, ISBN 978-3-030-02464-2
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-02465-9_39

Low Precision Processing for High Order Stencil Computations

Author(s): Gagandeep Singh, Dionysios Diamantopoulos, Sander Stuijk, Christoph Hagleitner, Henk Corporaal
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, 11733, 2019, Page(s) 403-415, ISBN 978-3-030-27561-7
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-27562-4_29

The Cost of Remembering

Author(s): Luca Gammaitoni, Igor Neri, Miquel López-Suárez, Davide Chiuchiù, Maria Cristina Diamantini
Published in: Proceedings of the 5th International Conference on Applications in Nonlinear Dynamics, 2019, Page(s) 1-8, ISBN 978-3-030-10891-5
Publisher: Springer International Publishing
DOI: 10.1007/978-3-030-10892-2_1

Datasets

Transprecision Computing (Micro-benchmarks)

Author(s): Borghesi, Andrea
Published in: Zenodo