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Open transPREcision COMPuting

Deliverables

Second summer school

Second summer school organized.

First summer school

First summer school organized.

Set up of intranet, data repository, and project management tool

OPRECOMP will make use of a web-based professional project management tool in order to facilitate the better management of all administrative, technical, and financial activities of the project.

Web-site and project logo

OPRECOMP public web-site and content, logo, presentation templates, and material for the identity of the project.

Initial data management plan

A first version of the data management plan will be released.

ReRAM and heterogeneous 3D-memory architecture models

The outputs of this deliverable are ReRAM and heterogeneous 3D-Memory models, which allow on different abstraction levels (from circuit to system level) explorations of appropriate memory architectures.

Initial report of embedded deep learning using transprecision computing

Report detailing the initial gains obtained by employing transprecision computing in deep learning applications

Evaluation results for heterogeneous memories

Report on the energy efficiency of heterogeneous memory hierarchies based on emerging memory technologies.

Simulation results for NEMS memory devices

Evaluation results of non-conventional NEMS memory devices will be provided by UNIPG.

Fundamental physics limits

Report that formalizes the fundamental physics limits of computation for logic gates and memory devices.

Initial report of big data applications using transprecision computing

Initial report on the Big Data application in T8.3 using the kW platform.

Evaluation of approximate computing techniques

The output of this deliverable is a quantification of the benefits of memorization, task elimination, loop perforation, randomized sparsification and sketching, and skipping memory accesses.

Final version of the algorithms

Report on the achieved gains attained with the new algorithms for data assimilation, linear algebra, graph analytics and the approximate computing.

Initial dissemination and exploitation plan report

Initial report on dissemination and exploitation. The report will include also a market analysis for the technology developed by OPRECOMP.

Processing unit for controllable precision

Specification of the processing unit with precision control that will be used in mW and kW range systems.

Intermediate applications progress report

Report describing all the progress made on all micro-benchmarks.

Definition of the hardware abstraction layer

Definition of the hardware abstraction layer that controls various precision configuration options of architectures.

Error-energy relations: fundamental limits

Report containing the analysis of the relation between minimum energy required for logic operation that depends on fundamental physical constrains.

Initial communication activity and plan report

A report on planned/completed communication activities will be provided.

Transprecision software stack design

An initial characterization of relevant applications and/or proxy benchmarks for these applications. The deliverable will present the initial design and elaboration of functionality of the software stack.

Numerical analysis of algorithms

Report that assesses the effect of transprecision computing on the algorithms.

Intermediate dissemination and exploitation plan report

Intermediate report on dissemination and exploitation. The report will include also a market analysis for the technology developed by OPRECOMP.

Prototype version of the algorithms

A report describing the advances attained with the algorithms during the initial refactoring phase.

Intermediate communication activity and plan report

A report on planned/completed communication activities will be provided.

Error-energy relations: technological limits

Report containing the analysis of the relation between minimum energy required for logic operation and result accuracy bounded by limits imposed by technology selected in WP4.

Numerical analysis of transprecision

Report that formalizes the extension of fundamental principles of numerical analysis to variable precision arithmetic.

Evaluation of transprecision

The output of this deliverable is a quantification of the benefits of transprecision (e.g., low precision floating-point vs fixed-point representation) and stochastic estimators on the five problem domains.

Error resilience

Report with a precise characterization of the algorithmic kernels to be targeted by the approximate computing techniques on the five problem domains.

Quality metrics

A concise definition of metrics to be used in the quality assessment of the solutions produced by the algorithms.

Initial report on micro-benchmarks

Initial report on the applications and micro-benchmarks selected for the project as well as the measured performance on state-of-the-art architectures.

Initial applications progress report

Report describing all the progress made on all micro-benchmarks.

Initial version of the kW pilot-platform

Initial working version of the HPC node. It will be used in WP8 to demonstrate the kW range apps.

Initial version of the mW pilot-platform

Initial working version of the mW platform. It will be used in WP8 to demonstrate the mW range apps.

Intermediate version of transprecision software stack

The initial version of the software stack will be early available for applications (WP7) and initial demonstrations (WP8). The final version will be used to make the final evaluations of the systems in the mW and kW range.

Initial version of transprecision software stack

The initial version of the software stack will be early available for applications (WP7) and initial demonstrations (WP8). The final version will be used to make the final evaluations of the systems in the mW and kW range.

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Publications

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Author(s): Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
Published in: IEEE Transactions on Circuits and Systems I: Regular Papers, Issue 64/9, 2017, Page(s) 2481-2494, ISSN 1549-8328
DOI: 10.1109/TCSI.2017.2698019

Flexible, Scalable and Energy Efficient Bio-Signals Processing on the PULP Platform: A Case Study on Seizure Detection

Author(s): Fabio Montagna, Simone Benatti, Davide Rossi
Published in: Journal of Low Power Electronics and Applications, Issue 7/2, 2017, Page(s) 16, ISSN 2079-9268
DOI: 10.3390/jlpea7020016

A machine learning approach for automated wide-range frequency tagging analysis in embedded neuromonitoring systems

Author(s): Fabio Montagna, Marco Buiatti, Simone Benatti, Davide Rossi, Elisabetta Farella, Luca Benini
Published in: Methods, Issue 129, 2017, Page(s) 96-107, ISSN 1046-2023
DOI: 10.1016/j.ymeth.2017.06.019

A Prosthetic Hand Body Area Controller Based on Efficient Pattern Recognition Control Strategies

Author(s): Simone Benatti, Bojan Milosevic, Elisabetta Farella, Emanuele Gruppioni, Luca Benini
Published in: Sensors, Issue 17/4, 2017, Page(s) 869, ISSN 1424-8220
DOI: 10.3390/s17040869

"A 2.2-<inline-formula> <tex-math notation=""LaTeX"">$\mu$ </tex-math> </inline-formula>W Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes"

Author(s): Giovanni Rovere, Schekeb Fateh, Luca Benini
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Issue 8/3, 2018, Page(s) 543-554, ISSN 2156-3357
DOI: 10.1109/JETCAS.2018.2828505

Look-ahead in the two-sided reduction to compact band forms for symmetric eigenvalue problems and the SVD

Author(s): Rafael Rodríguez-Sánchez, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Andrés E. Tomás
Published in: Numerical Algorithms, Issue 80/2, 2019, Page(s) 635-660, ISSN 1017-1398
DOI: 10.1007/s11075-018-0500-8

FlexFloat: A Software Library for Transprecision Computing

Author(s): Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Issue December 2018, 2018, Page(s) 1-1, ISSN 0278-0070
DOI: 10.1109/TCAD.2018.2883902

NEURA ghe

Author(s): Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
Published in: ACM Transactions on Reconfigurable Technology and Systems, Issue 11/3, 2018, Page(s) 1-24, ISSN 1936-7406
DOI: 10.1145/3284357

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation flow for Near-Sensor Ultra-low Power Processing

Author(s): Satyajit Das, Kevin J. M. Martin, Davide Rossi, Philippe Coussy, Luca Benini
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, Page(s) 1-1, ISSN 0278-0070
DOI: 10.1109/TCAD.2018.2834397

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Author(s): Fabian Schuiki, Michael Schaffner, Frank K. Gurkaynak, Luca Benini
Published in: IEEE Transactions on Computers, Issue 68/4, 2019, Page(s) 484-497, ISSN 0018-9340
DOI: 10.1109/tc.2018.2876312

The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores

Author(s): Igor Loi, Alessandro Capotondi, Davide Rossi, Andrea Marongiu, Luca Benini
Published in: IEEE Transactions on Multi-Scale Computing Systems, Issue 4/2, 2018, Page(s) 99-112, ISSN 2332-7766
DOI: 10.1109/TMSCS.2017.2769046

A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters

Author(s): Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini
Published in: IEEE Embedded Systems Letters, Issue 9/4, 2017, Page(s) 125-128, ISSN 1943-0663
DOI: 10.1109/LES.2017.2707978

A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems

Author(s): Victor Javier Kartsch, Simone Benatti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini
Published in: Information Fusion, Issue 43, 2018, Page(s) 66-76, ISSN 1566-2535
DOI: 10.1016/j.inffus.2017.11.005

Cost of remembering a bit of information

Author(s): D. Chiuchiù, M. López-Suárez, I. Neri, M. C. Diamantini, L. Gammaitoni
Published in: Physical Review A, Issue 97/5, 2018, Page(s) Phys. Rev. A 97, 052108, ISSN 2469-9926
DOI: 10.1103/PhysRevA.97.052108

Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes

Author(s): Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini
Published in: IEEE Transactions on Parallel and Distributed Systems, Issue 29/2, 2018, Page(s) 420-434, ISSN 1045-9219
DOI: 10.1109/TPDS.2017.2752706

Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine

Author(s): Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Issue 9/2, 2019, Page(s) 309-322, ISSN 2156-3357
DOI: 10.1109/JETCAS.2019.2905654

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform using Hyperdimensional Computing

Author(s): Benatti, Simone; Montagna, Fabio; Kartsch, Victor; Rahimi, Abbas; id_orcid0000-0003-3141-4970; Rossi, Davide; Benini, Luca; id_orcid0000-0001-8068-3806
Published in: IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 13 (3), Issue 1, 2019, Page(s) 516-528, ISSN 1940-9990
DOI: 10.3929/ethz-b-000339838

Toward a modular precision ecosystem for high-performance computing

Author(s): Hartwig Anzt, Goran Flegar, Thomas Grützmacher, Enrique S Quintana-Ortí
Published in: The International Journal of High Performance Computing Applications, 2019, Page(s) 109434201984654, ISSN 1094-3420
DOI: 10.1177/1094342019846547

Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing

Author(s): Antonio Pullini, Davide Rossi, Igor Loi, Giuseppe Tagliavini, Luca Benini
Published in: IEEE Journal of Solid-State Circuits, Issue 54/7, 2019, Page(s) 1970-1981, ISSN 0018-9200
DOI: 10.1109/jssc.2019.2912307

Significance-Driven Data Truncation for Preventing Timing Failures

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: IEEE Transactions on Device and Materials Reliability, Issue 19/1, 2019, Page(s) 25-36, ISSN 1530-4388
DOI: 10.1109/tdmr.2019.2898949

Dynamic look-ahead in the reduction to band form for the singular value decomposition

Author(s): Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Rocío Carratalá-Sáez, Enrique S. Quintana-Ortí
Published in: Parallel Computing, Issue 81, 2019, Page(s) 22-31, ISSN 0167-8191
DOI: 10.1016/j.parco.2018.11.001

Variable-size batched Gauss–Jordan elimination for block-Jacobi preconditioning on graphics processors

Author(s): Hartwig Anzt, Jack Dongarra, Goran Flegar, Enrique S. Quintana-Ortí
Published in: Parallel Computing, Issue 81, 2019, Page(s) 131-146, ISSN 0167-8191
DOI: 10.1016/j.parco.2017.12.006

Energy-Efficient Iterative Refinement Using Dynamic Precision

Author(s): JunKyu Lee, Hans Vandierendonck, Mahwish Arif, Gregory D. Peterson, Dimitrios S. Nikolopoulos
Published in: IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Issue 8/4, 2018, Page(s) 722-735, ISSN 2156-3357
DOI: 10.1109/jetcas.2018.2850665

Integrating DRAM power-down modes in gem5 and quantifying their impact

Author(s): Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '17, 2017, Page(s) 86-95
DOI: 10.1145/3132402.3132444

Using run-time reverse-engineering to optimize DRAM refresh

Author(s): Deepak M. Mathew, Éder F. Zulian, Matthias Jung, Kira Kraft, Christian Weis, Bruce Jacob, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '17, 2017, Page(s) 115-124
DOI: 10.1145/3132402.3132419

Balanced CSR Sparse Matrix-Vector Product on Graphics Processors

Author(s): Goran Flegar, Enrique S. Quintana-Ortí
Published in: Euro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 – September 1, 2017, Proceedings, 2017, Page(s) 697-709
DOI: 10.1007/978-3-319-64203-1_50

Impact of temporal subsampling on accuracy and performance in practical video classification

Author(s): F. Scheidegger, L. Cavigelli, M. Schaffner, A. C. I. Malossi, C. Bekas, L. Benini
Published in: 2017 25th European Signal Processing Conference (EUSIPCO), 2017, Page(s) 996-1000
DOI: 10.23919/EUSIPCO.2017.8081357

Variable-Size Batched LU for Small Matrices and Its Integration into Block-Jacobi Preconditioning

Author(s): Hartwig Anzt, Jack Dongarra, Goran Flegar, Enrique S. Quintana-Orti
Published in: 2017 46th International Conference on Parallel Processing (ICPP), 2017, Page(s) 91-100
DOI: 10.1109/ICPP.2017.18

Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis

Author(s): Lei Li, Michael Gautschi, Luca Benini
Published in: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Issue 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017), Thessaloniki, Greece, September 25-27, 2017, 2017, Page(s) 1-8
DOI: 10.1109/PATMOS.2017.8106987

A sub-10mW real-time implementation for EMG hand gesture recognition based on a multi-core biomedical SoC

Author(s): Simone Benatti, Giovanni Rovere, Jonathan Bosser, Fabio Montagna, Elisabetta Farella, Horian Glaser, Philipp Schonle, Thomas Burger, Schekeb Fateh, Qiuting Huang, Luca Benini
Published in: 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 2017, Page(s) 139-144
DOI: 10.1109/IWASI.2017.7974234

Work-in-Progress: Quantized NNs as the Definitive Solution for Inference on Low-Power ARM MCUs?

Author(s): Manuele Rusci, Alessandro Capotondi, Francesco Conti, Luca Benini
Published in: 2018 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Issue November 2018, 2018, Page(s) 1-2
DOI: 10.1109/CODESISSS.2018.8525915

A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing

Author(s): Stefan Mach, Davide Rossi, Giuseppe Tagliavini, Andrea Marongiu, Luca Benini
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/ISCAS.2018.8351816

Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?

Author(s): Manuele Rusci, Lukas Cavigelli, Luca Benini
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/ISCAS.2018.8351807

A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics

Author(s): Satyajit Das, Kevin J. M. Martin, Philippe Coussy, Davide Rossi
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/ISCAS.2018.8351749

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

Author(s): Andreas Kurth, Pirmin Vogel, Andrea Marongiu, Luca Benini
Published in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, Page(s) 292-300
DOI: 10.1109/iccd.2018.00052

An Energy-Efficient IoT node for HMI applications based on an ultra-low power Multicore Processor

Author(s): Victor Kartsch, Marco Guermandi, Simone Benatti, Fabio Montagna, Luca Benini
Published in: 2019 IEEE Sensors Applications Symposium (SAS), 2019, Page(s) 1-6
DOI: 10.1109/SAS.2019.8705984

Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster

Author(s): Di Mauro, Alfio; Rossi, Davide; Pullini, Antonio; Flatresse, Philippe; Benini, Luca; id_orcid0000-0001-8068-3806
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Issue 1, 2018
DOI: 10.3929/ethz-b-000314386

Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX

Author(s): Schiavone, Pasquale D.; Rossi, Davide; Pullini, Antonio; Di Mauro, Alfio; Conti, Francesco; id_orcid0000-0002-7924-933X; Benini, Luca
Published in: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Issue 1, 2018
DOI: 10.3929/ethz-b-000314427

High-Performance GPU Implementation of PageRank with Reduced Precision Based on Mantissa Segmentation

Author(s): Thomas Grutzmacher, Hartwig Anzt, Florian Scheidegger, Enrique S. Quintana-Orti
Published in: 2018 IEEE/ACM 8th Workshop on Irregular Applications: Architectures and Algorithms (IA3), 2018, Page(s) 61-68
DOI: 10.1109/IA3.2018.00015

HelmGemm: Managing GPUs and FPGAs for transprecision GEMM workloads in containerized environments

Author(s): Dionysios Diamantopoulos, Christoph Hagleitner
Published in: 2019

An In-DRAM Neural Network Processing Engine

Author(s): Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5
DOI: 10.1109/iscas.2019.8702458

A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping

Author(s): Dionysios Diamantopoulos, Christoph Hagleitner
Published in: 2018 International Conference on Field-Programmable Technology (FPT), 2018, Page(s) 338-341
DOI: 10.1109/fpt.2018.00068

Efficient coding scheme for DDR4 memory subsystems

Author(s): Kira Kraft, Deepak M. Mathew, Chirag Sudarshan, Matthias Jung, Christian Weis, Norbert Wehn, Florian Longnos
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '18, 2018, Page(s) 148-157
DOI: 10.1145/3240302.3240424

Driving into the memory wall - the role of memory for advanced driver assistance systems and autonomous driving

Author(s): Matthias Jung, Sally A. McKee, Chirag Sudarshan, Christoph Dropmann, Christian Weis, Norbert Wehn
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '18, 2018, Page(s) 377-386
DOI: 10.1145/3240302.3240322

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment - Case Study on a Floating-Point Unit

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: Proceedings of the International Symposium on Low Power Electronics and Design - ISLPED '18, 2018, Page(s) 1-6
DOI: 10.1145/3218603.3218617

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Author(s): Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
Published in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), 2018, Page(s) 171-176
DOI: 10.1109/iolts.2018.8474084

The Role of Memories in Transprecision Computing

Author(s): Christian Weis, Matthias Jung, Eder F. Zulian, Chirag Sudarshan, Deepak M. Mathew, Norbert Wehn
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351768

ecTALK: Energy efficient coherent transprecision accelerators — The bidirectional long short-term memory neural network case

Author(s): Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner
Published in: 2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2018, Page(s) 1-3
DOI: 10.1109/coolchips.2018.8373077

Fast Blocking of Householder Reflectors on Graphics Processors

Author(s): Andres E. Tomas Dominguez, Enrique S. Quintana Orti
Published in: 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), 2018, Page(s) 385-393
DOI: 10.1109/pdp2018.2018.00068

Extending the POWER Architecture with Transprecision Co-Processors

Author(s): Heiner Giefers, Dionysios Diamantopoulos
Published in: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, Page(s) 1-5
DOI: 10.1109/iscas.2018.8351755

Reduction to Band Form for the Singular Value Decomposition on Graphics Accelerators

Author(s): Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Enrique S. Quintana-Ortí
Published in: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores - PMAM'18, 2018, Page(s) 51-60
DOI: 10.1145/3178442.3178448

Cholesky and Gram-Schmidt Orthogonalization for Tall-and-Skinny QR Factorizations on Graphics Processors

Author(s): Andrés E. Tomás, Enrique S. Quintana-Ortí
Published in: Euro-Par 2019: Parallel Processing - 25th International Conference on Parallel and Distributed Computing, Göttingen, Germany, August 26–30, 2019, Proceedings, Issue 11725, 2019, Page(s) 469-480
DOI: 10.1007/978-3-030-29400-7_33

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Author(s): Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Issue 11733, 2019, Page(s) 34-47
DOI: 10.1007/978-3-030-27562-4_3

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing

Author(s): Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Issue 11733, 2019, Page(s) 429-441
DOI: 10.1007/978-3-030-27562-4_31

Residual Replacement in Mixed-Precision Iterative Refinement for Sparse Linear Systems

Author(s): Hartwig Anzt, Goran Flegar, Vedran Novaković, Enrique S. Quintana-Ortí, Andrés E. Tomás
Published in: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, Issue 11203, 2018, Page(s) 554-561
DOI: 10.1007/978-3-030-02465-9_39

Low Precision Processing for High Order Stencil Computations

Author(s): Gagandeep Singh, Dionysios Diamantopoulos, Sander Stuijk, Christoph Hagleitner, Henk Corporaal
Published in: Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7–11, 2019, Proceedings, Issue 11733, 2019, Page(s) 403-415
DOI: 10.1007/978-3-030-27562-4_29