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Computation-in-memory architecture based on resistive devices

Deliverables

First version programming interface at the micro- and macro-levels

Description of micro and macro instruction set.

Initial memristor crossbar based logic/ arithmetic and memory designs and models

The memory compiler models of IMEC will incorporate a few most promising non-volatile memory models, together with behavioural models for sense amplifiers and column/row decoder circuits. These models therefore overcome the limitations of NVSim by generating power/performance/area data which can be applied to a wide range of in-memory computing architecture exploration.

Initial communication protocols and infrastructure

In this report, we will detail the results that will describe the circuits and methods to allow efficient data transfer between tiles and the outside world. The report will detail the challenges, and list the potential solutions that were considered. The circuits methods described in this report will form the basis of the initial system being developed I the project, which will then be refined throughout the project.

First version backend compiler for micro-instructions

First compiler generation of micro instruction for the CIM file.

Initial models of memristive device

Based on experimental memristive device characteristics and existing physical device models that are mainly based on continuum models, physical and/or behavioural compact models will be derived for use in circuit simulation. This activity includes model building for both ReRAM devices (RTWH) and PCM devices (IBM), while IMEC will bring in their models as “blackboxes”.

Report on targeted applications, their specifications, requirements

The report will describe some highly relevant problems arising in the emerging fields of cognitive computing and internet of things (IoT) that could benefit from implementation on non-von Neumann computing architecture based on the computation-in-memory (CIM) dies. The CIM dies could implement digital memristive logic or perform certain arithmetic operations such as vector-matrix multiplication. The report will also describe the application-specific requirements on the CIM dies.

Initial CIM microarchitecture

To enable the technology-aware microarchitecture simulator framework for detailed in-memory computing trade-off exploration, in WP4 a bridge has to be created between the macro-architecture simulator developed as part of WP 3 and the memory compiler models from D4.4.

First report on new algorithmic solutions

Develop new algorithms for the targeted applications while considering the features of the new CIM architecture.

Initial macro CIM architecture and CIM-ISA

Initial ISA description for the whole CIM architecture based on the requirements from D1.1

Promotional material

Material for publicity and promotion including a project leaflet, a poster, a powerpoint presentation and a short film.

Project website

A project website will be designed, including an external facing website and an internal facing secure cloud storage.

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Publications

Compressed Sensing With Approximate Message Passing Using In-Memory Computing

Author(s): Manuel Le Gallo, Abu Sebastian, Giovanni Cherubini, Heiner Giefers, Evangelos Eleftheriou
Published in: IEEE Transactions on Electron Devices, 2018, Page(s) 1-9, ISSN 0018-9383
DOI: 10.1109/TED.2018.2865352

A phase-change memory model for neuromorphic computing

Author(s): S. R. Nandakumar, Manuel Le Gallo, Irem Boybat, Bipin Rajendran, Abu Sebastian, Evangelos Eleftheriou
Published in: Journal of Applied Physics, Issue 124/15, 2018, Page(s) 152135, ISSN 0021-8979
DOI: 10.1063/1.5042408

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing

Author(s): Simone Benatti, Fabio Montagna, Victor Kartsch, Abbas Rahimi, Davide Rossi, Luca Benini
Published in: IEEE Transactions on Biomedical Circuits and Systems, Issue 13/3, 2019, Page(s) 516-528, ISSN 1932-4545
DOI: 10.1109/tbcas.2019.2914476

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Author(s): Schmuck, Manuel; Benini, Luca; Rahimi, Abbas
Published in: ACM Journal on Emerging Technologies in Computing Systems, Issue 4, 2019, ISSN 1550-4832
DOI: 10.3929/ethz-b-000338354

Hyperdimensional Computing with Local Binary Patterns: One-shot Learning for Seizure Onset Detection and Identification of Ictogenic Brain Regions from Short-time iEEG Recordings

Author(s): Alessio Burrello, Kaspar Anton Schindler, Luca Benini, Abbas Rahimi
Published in: IEEE Transactions on Biomedical Engineering, 2019, Page(s) 1-1, ISSN 0018-9294
DOI: 10.1109/tbme.2019.2919137

The Next 700 Accelerated Layers

Author(s): Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary Devito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
Published in: ACM Transactions on Architecture and Code Optimization, Issue 16/4, 2019, Page(s) 1-26, ISSN 1544-3566
DOI: 10.1145/3355606

Flextended Tiles

Author(s): Jie Zhao, Albert Cohen
Published in: ACM Transactions on Architecture and Code Optimization, Issue 16/4, 2019, Page(s) 1-25, ISSN 1544-3566
DOI: 10.1145/3369382

Analyses of a 1-layer neuromorphic network using memristive devices with non-continuous resistance levels

Author(s): A. Siemon, S. Ferch, A. Heittmann, R. Waser, D. J. Wouters, S. Menzel
Published in: APL Materials, Issue 7/9, 2019, Page(s) 091110, ISSN 2166-532X
DOI: 10.1063/1.5108658

Exploiting the switching dynamics of HfO 2 -based ReRAM devices for reliable analog memristive behavior

Author(s): F. Cüppers, S. Menzel, C. Bengel, A. Hardtdegen, M. von Witzleben, U. Böttger, R. Waser, S. Hoffmann-Eifert
Published in: APL Materials, Issue 7/9, 2019, Page(s) 091105, ISSN 2166-532X
DOI: 10.1063/1.5108654

Applications of Computation-In-Memory Architectures based on Memristive Devices

Author(s): Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando G. Redondo, G. Karunaratne, Abbas Rahimi, Luca Benini
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 486-491
DOI: 10.23919/DATE.2019.8715020

Time-division Multiplexing Automata Processor

Author(s): Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Published in: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, Page(s) 794-799
DOI: 10.23919/date.2019.8715140

Memristive Device Based Circuits for Computation-in-Memory Architectures

Author(s): Muath Abu Lebdeh, Uljana Reinsalud, Hoang Anh Du Nguyen, Stephan Wong, Said Hamdioui
Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5
DOI: 10.1109/iscas.2019.8702542

One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing

Author(s): Alessio Burrello, Kaspar Schindler, Luca Benini, Abbas Rahimi
Published in: 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2018, Page(s) 1-4
DOI: 10.1109/BIOCAS.2018.8584751

Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory

Author(s): Anne Siemon, Dirk Wouters, Said Hamdioui, Stephan Menzel
Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, Page(s) 1-5
DOI: 10.1109/iscas.2019.8702600

Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms

Author(s): Burrello, Alessio; Cavigelli, Lukas; id_orcid0000-0003-1767-7715; Schindler, Kaspar; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Published in: Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Issue 4, 2019
DOI: 10.3929/ethz-b-000307983

Towards Efficient Code Generation for Exposed Datapath Architectures

Author(s): Kanishkan Vadivel, Roel Jordans, Sander Stujik, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala
Published in: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Page(s) 86-89
DOI: 10.1145/3323439.3323990

CIM-SIM - Computation In Memory SIMuIator

Author(s): Ali BanaGozar, Kanishkan Vadivel, Sander Stuijk, Henk Corporaal, Stephan Wong, Muath Abu Lebdeh, Jintao Yu, Said Hamdioui
Published in: Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems - SCOPES '19, 2019, Page(s) 1-4
DOI: 10.1145/3323439.3323989

Memristive devices for computation-in-memory

Author(s): Jintao Yu, Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui
Published in: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, Page(s) 1646-1651
DOI: 10.23919/date.2018.8342278

Training DNN IoT Applications for Deployment On Analog NVM Crossbars

Author(s): Fernando García-Redondo, Shidhartha Das, Glen Rosendale
Published in: 2019

A computation-in-memory accelerator based on resistive devices

Author(s): Hoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Published in: Proceedings of the International Symposium on Memory Systems - MEMSYS '19, 2019, Page(s) 19-32
DOI: 10.1145/3357526.3357554

Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme

Author(s): Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Published in: 2019

TC-CIM: Empowering Tensor Comprehensions for Computation in Memory

Author(s): Andi Drebes, Lorenzo Chelini, Oleksandr Zinenko, Albert Cohen, Henk Corporaal, Tobias Grosser, Kanishkan Vadivel, Nicolas Vasilache
Published in: 2020

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics

Author(s): Matthew Douthwaite, Fernando Garcia-Redondo, Pantelis Georgiou, Shidhartha Das
Published in: 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2019, Page(s) 1-4
DOI: 10.1109/BIOCAS.2019.8919190

Evolvable Hyperdimensional Computing: Unsupervised Regeneration of Associative Memory to Recover Faulty Components

Author(s): Hersche, Michael; id_orcid0000-0003-3065-7639; Sangalli, Sara; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Published in: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Issue 2, 2020
DOI: 10.3929/ethz-b-000387115

Binary Models for Motor-Imagery Brain–Computer Interfaces: Sparse Random Projection and Binarized SVM

Author(s): Hersche, Michael; id_orcid0000-0003-3065-7639; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Published in: 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Issue 1, 2020
DOI: 10.3929/ethz-b-000387116

Compressing Subject-specific Brain–Computer Interface Models into One Model by Superposition in Hyperdimensional Space

Author(s): Hersche, Michael; id_orcid0000-0003-3065-7639; Rupp, Philipp; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Published in: Design, Automation and Test in Europe (DATE 2020), Issue 1, 2020
DOI: 10.3929/ethz-b-000387117

Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractions

Author(s): Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary DeVito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
Published in: Computing Research Repository (CoRR), 2018