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DESIGN OF EXTREMELY ENERGY-EFFICIENT MULTI-CORE PROCESSOR IN NANOSCALE CMOS FOR MEDIA PROCESSING IN PORTABLE DEVICES

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Parallel processing with less energy

Parallel processing in which multiple processors perform operations in different subsets of data is critical for many multimedia applications. A new chip architecture employing smart energy management schemes could slash energy consumption of portable devices.

Energy

Many future multimedia applications are naturally highly parallel and process massive data sets. As a simple example, an average of 1 000 000 numbers can be computed by averaging 1 000 sets of 1 000 numbers and then taking the average of those 1 000 averages. The EU-funded project RAVEN10 was launched to develop highly energy-efficient data-parallel many-core architectures supporting very small technology nodes (on the nano scale) for such applications. Importantly, on-chip dynamic reconfiguration control slashes fabrication costs that can amount to tens of millions of euros for modern single-application chips. To achieve their goals, scientists exploited dynamic voltage and frequency scaling (DVFS) schemes. DVFS is a power and heat management technique that adapts the voltage or frequency of the processor according to computational need. The RAVEN architecture, or Resilient Architecture with Vector-thread Execution, applies such schemes individually to each core with an independent control processor. The team successfully employed reconfigurable switched-capacitor (SC) DC-DC converters, a subset of DC-DC power converters that efficiently convert one voltage to another. However, certain technical issues needed resolution to maintain fine-grained DVFS schemes with a large numbers of processors. Adaptive clock schemes turned the SC loss associated with the output resistance of the converter to an advantage. Scientists achieved lower switching frequency and very high conversion efficiencies. In addition, conducting the system energy analysis for a changeable rather than fixed supply voltage enabled global optimisation. The system utilises the minimum energy point for each processor in each individual task. An innovative solution to the finite number of conversion ratios reduced energy per core up to 25 % compared to DVFS schemes with conventional voltage regulators. A test chip featuring a complete DVFS scheme implemented on a single core is currently under evaluation. Successful implementation of the RAVEN concept will drastically reduce the energy consumption and price of video and speech processing on cell phones and tablets with on-chip dynamic reconfiguration control. Potential annual energy savings from cell phones of just one brand could be the equivalent of that of tens of thousands of households — not bad considering the number of portable devices in use around the world.

Keywords

Processing, portable devices, energy-efficient, nano scale, on-chip, DVFS

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