Low-cost, high-tech circuit fabrication for SMEs
Even for those too young to remember the first computers and televisions, the phenomenon of the amazing, shrinking consumer electronics device is well known to all. As parts and components become ever smaller, now reaching the dimensions of single atoms and molecules (nano-scale), their fabrication becomes increasingly difficult – and often costly. Producing miniaturised electronic circuits is commonly done with the so-called top-down photolithographic (PL) method. A pattern on a template is transferred to a surface (substrate) using light to ‘trace’ the pattern in photo-responsive materials already deposited on the substrate. PL equipment is extremely expensive, on the order of EUR 65 million for a single system, making it cost-prohibitive for many small and medium-sized enterprises (SMEs). Potential solutions to the cost issue have focused on bottom-up techniques to form the nano-scale patterns required of today’s microelectronics. Currently, bottom-up technology employing self-assembly of molecules to form patterns is promising but regularity and alignment over large areas is problematic. That may be about to change. Block co-polymers (BCPs) are long-chain molecules made up of two or more repeating units that individually repeat in ‘blocks’ (for example, -X-X-X-Y-Y-Y-). They have attracted considerable attention for decades due to their ability to self-assemble into ordered nanostructures of various morphologies in precisely defined positions and over large areas. The EU-funded ‘Large area molecularly assembled nanopatterns for devices’ (Lamand) project is focused on developing a combination of bottom-up and top-down technology for nanofabrication of information communication technology (ICT) components using BCP methodology. Scientists have generated aligned, low-defect BCP nanopatterns with dimensions in the range of 10 to 40 nanometres. They have also produced nanowire arrays via templates. Modification of substrate surfaces with self-assembled layers has enabled optimal surface pattern coverage and orientation. Advanced validation test methods developed or adapted for the project employ microscopy and X-ray techniques, image simulation and electrical properties characterisation. Technology being developed by the Lamand consortium has the potential to dramatically increase the competitiveness of European SMEs in the microelectronics sector by providing affordable and reliable nanopatterning technology for ICT components.
