Periodic Reporting for period 2 - YESvGaN (Vertical GaN on Silicon: Wide Band Gap Power at Silicon Cost)
Reporting period: 2022-05-01 to 2023-04-30
For the economical as well as ecological future of Europe it is widely agreed upon that energy savings and management are ground challenges. Since almost 50 % of the used energy worldwide is electric, it is important to distribute and use electric energy in the most efficient manner. In this context, power transistors based on wide band gap (WBG) materials such as gallium nitride (GaN) and silicon carbide (SiC) are a central technology to enhance efficiency in power electronic systems by replacing currently used silicon (Si)-based power switches for a variety of applications and markets, such as electric vehicles, power supplies, industrial drives for electric motors or photovoltaic inverters.
However, existing lateral GaN power transistors are limited in their power handling capability while vertical SiC transistors cannot compete with the established silicon regarding their cost. To that end, 23 European partners from research to industry joined their semiconductor and power electronics expertise in YESvGaN for an ambitious goal: to establish a new class of power transistors based on GaN, which combines the efficiency of WBG semiconductors with the cost benefits of Si technology. This will be enabled by innovative vertical transistor architectures on heteroepitaxial GaN layers on low-cost substrates. For this, new developments are required along the whole value chain, which are addressed by the following project objectives:
- Development of vertical drift epitaxy up to 1200 V blocking voltage on low-cost silicon or sapphire substrates up to 300 mm wafer size
- Development of low-cost, vertical GaN power transistors and process technology with performance above state-of-the-art SiC MOSFETs at chip costs competitive with Si IGBTs
- Development of membrane process technology for vertical GaN power transistors with ultra-low resistance contribution from the backside contact
- Development of advanced interconnection technology compatible with membrane vertical GaN power transistors and evaluation of their reliability based on ECPE Guideline AQG324
- Understanding performance limitations, degradation and failure mechanisms of membrane vertical GaN power transistors from chip to device
- Delivery of a datasheet for membrane vertical GaN power transistors with full static and dynamic behaviour. Improvement of system efficiency by reducing losses up to 50% and by increasing power density by 15% (compared to silicon) for the chosen technology demonstrators of high-power converters in order to increase their cost efficiency.
However, existing lateral GaN power transistors are limited in their power handling capability while vertical SiC transistors cannot compete with the established silicon regarding their cost. To that end, 23 European partners from research to industry joined their semiconductor and power electronics expertise in YESvGaN for an ambitious goal: to establish a new class of power transistors based on GaN, which combines the efficiency of WBG semiconductors with the cost benefits of Si technology. This will be enabled by innovative vertical transistor architectures on heteroepitaxial GaN layers on low-cost substrates. For this, new developments are required along the whole value chain, which are addressed by the following project objectives:
- Development of vertical drift epitaxy up to 1200 V blocking voltage on low-cost silicon or sapphire substrates up to 300 mm wafer size
- Development of low-cost, vertical GaN power transistors and process technology with performance above state-of-the-art SiC MOSFETs at chip costs competitive with Si IGBTs
- Development of membrane process technology for vertical GaN power transistors with ultra-low resistance contribution from the backside contact
- Development of advanced interconnection technology compatible with membrane vertical GaN power transistors and evaluation of their reliability based on ECPE Guideline AQG324
- Understanding performance limitations, degradation and failure mechanisms of membrane vertical GaN power transistors from chip to device
- Delivery of a datasheet for membrane vertical GaN power transistors with full static and dynamic behaviour. Improvement of system efficiency by reducing losses up to 50% and by increasing power density by 15% (compared to silicon) for the chosen technology demonstrators of high-power converters in order to increase their cost efficiency.
Building on the results from the first project periods, the individual building blocks needed to realize fully functional vertical GaN membrane transistors were on the one hand improved and on the other hand consequently integrated into full processes. The main activities and achievements of the 2nd project year per work-package (WP) are summarized below.
WP2 Epitaxy
- Increase of drift layer thickness for heteroepitaxial stacks grown on silicon and sapphire and improvement of doping control to increase blocking voltage. High blocking voltage for hard breakdown beyond 650 V and 920 V on silicon and sapphire, respectively. Avalanche breakdown shown on sapphire which is a novelty for heteroepitaxial GaN.
- Advanced epitaxial layer characterization techniques (XRT, KPFM and Raman) applied to GaN membrane layers (substrate previously removed) showing that substrate removal process results in undamaged membranes.
- An MOCVD reactor for 300 mm GaN-on-silicon growth was successfully installed and showed superior homogeneity for the growth of first HEMT structures.
WP3 Chip technology
- Continuous improvement of the process modules for Trench Gate MOSFETs (e.g. channel mobility 17 cm2/Vs), Planar Gate MOSFETs and FinFETs.
- Confirmation of the advantages of a mixed plasma and thermal ALD for the gate dielectric of vertical GaN FinFETs using a detailed in-vacuo XPS study
- Calibration of implantation profiles for Mg implantation into GaN combined with a study on wafer damage using XRD and IR-ellipsometry.
- Design phase for a 200mm implanter for implantation into wide band gap materials (GaN and SiC) finished and parts ordered for its assembly.
- Wafer-level characterization of transistor and capacitor test structures to calibrate TCAD models
WP4 Membrane processing
- Transfer of process modules for local substrate and epitaxial buffer removal for GaN-on-Si wafers to 200 mm in an industrial line.
- Ohmic contacts to the nitrogan-face of GaN membranes thanks to an advanced lithographic process.
- Demonstration of a complete backside process on full 150 mm GaN-on-Si wafers to fabricate fully vertical Schottky diodes.
WP5 AIT and reliability
- Testing of different die attach methods (soldering, sintering, face-down sintering, nanowiring, sintering to inverted substrates, ceramic embedding) for GaN-on-Si membrane chips.
- Successful die attach for Schottky-diodes where the diodes characteristic could preserved
- Wire bonding with successful pull tests to membranes
- Thermal characterization of membranes by thermal reflectance spectroscopy, scanning thermal microscopy and micro-Raman spectroscopy.
WP6 Application
- Design and fabrication of a low inductive half-bridge power module (HBPM) which can integrate bare dies or discrete devices and will be used for benchmarking YESvGaN vertical GaN transistors to existing silicon carbide transistors.
- Testing and characterization of the power module with available silicon carbide chips and its integration into demonstrator applications.
WP1 ‘Project Management’ and WP7 ‘Dissemination and Exploitation’ are transversal WPs organizing the work inside the project and establishing suitable communication channels to disseminate the results. YESvGaN results have been disseminated via a range of conference talks, social media posts (Twitter, LinkedIn channel), lectures of YESvGaN members at a summer school in Brixen in 2022 (video recordings available on the YESvGaN Youtube channel) and participation to fairs. A dedicated YESvGaN summerschool has been organized which will take place in August 2023 in Ghent in cooperation with two other European projects (TRANSFORM and PowerElec).
WP2 Epitaxy
- Increase of drift layer thickness for heteroepitaxial stacks grown on silicon and sapphire and improvement of doping control to increase blocking voltage. High blocking voltage for hard breakdown beyond 650 V and 920 V on silicon and sapphire, respectively. Avalanche breakdown shown on sapphire which is a novelty for heteroepitaxial GaN.
- Advanced epitaxial layer characterization techniques (XRT, KPFM and Raman) applied to GaN membrane layers (substrate previously removed) showing that substrate removal process results in undamaged membranes.
- An MOCVD reactor for 300 mm GaN-on-silicon growth was successfully installed and showed superior homogeneity for the growth of first HEMT structures.
WP3 Chip technology
- Continuous improvement of the process modules for Trench Gate MOSFETs (e.g. channel mobility 17 cm2/Vs), Planar Gate MOSFETs and FinFETs.
- Confirmation of the advantages of a mixed plasma and thermal ALD for the gate dielectric of vertical GaN FinFETs using a detailed in-vacuo XPS study
- Calibration of implantation profiles for Mg implantation into GaN combined with a study on wafer damage using XRD and IR-ellipsometry.
- Design phase for a 200mm implanter for implantation into wide band gap materials (GaN and SiC) finished and parts ordered for its assembly.
- Wafer-level characterization of transistor and capacitor test structures to calibrate TCAD models
WP4 Membrane processing
- Transfer of process modules for local substrate and epitaxial buffer removal for GaN-on-Si wafers to 200 mm in an industrial line.
- Ohmic contacts to the nitrogan-face of GaN membranes thanks to an advanced lithographic process.
- Demonstration of a complete backside process on full 150 mm GaN-on-Si wafers to fabricate fully vertical Schottky diodes.
WP5 AIT and reliability
- Testing of different die attach methods (soldering, sintering, face-down sintering, nanowiring, sintering to inverted substrates, ceramic embedding) for GaN-on-Si membrane chips.
- Successful die attach for Schottky-diodes where the diodes characteristic could preserved
- Wire bonding with successful pull tests to membranes
- Thermal characterization of membranes by thermal reflectance spectroscopy, scanning thermal microscopy and micro-Raman spectroscopy.
WP6 Application
- Design and fabrication of a low inductive half-bridge power module (HBPM) which can integrate bare dies or discrete devices and will be used for benchmarking YESvGaN vertical GaN transistors to existing silicon carbide transistors.
- Testing and characterization of the power module with available silicon carbide chips and its integration into demonstrator applications.
WP1 ‘Project Management’ and WP7 ‘Dissemination and Exploitation’ are transversal WPs organizing the work inside the project and establishing suitable communication channels to disseminate the results. YESvGaN results have been disseminated via a range of conference talks, social media posts (Twitter, LinkedIn channel), lectures of YESvGaN members at a summer school in Brixen in 2022 (video recordings available on the YESvGaN Youtube channel) and participation to fairs. A dedicated YESvGaN summerschool has been organized which will take place in August 2023 in Ghent in cooperation with two other European projects (TRANSFORM and PowerElec).
YESvGaN develops a new class of power transistors based on gallium nitride (GaN) for efficient and affordable power conversion. This is enabled by an innovative membrane transistor approach, which allows fabricating vertical GaN transistors for high voltage and high current operations as well as employing inexpensive semiconductor substrates. The target technology can replace current Si-based insulated gate bipolar transistors (IGBTs) due to its comparable cost level while operating at the high efficiency of silicon carbide (SiC) field effect transistors (FETs).
YESvGaN offers the following advancements and novelties beyond the state of the art:
- Demonstrating a new vertical GaN power device architecture offering WBG performance on a low-cost substrate.
- Developing high current vertical GaN power devices for up to 1200 V/100 A voltage class.
- Providing the assembly and interconnection technology for vertical GaN power switches making them as reliable as currently used power switches.
- Enabling lower cost in high power density applications (e.g. traction inverter) especially for high volume applications.
- Provide the material and equipment for future production of the here developed devices.
YESvGaN offers the following advancements and novelties beyond the state of the art:
- Demonstrating a new vertical GaN power device architecture offering WBG performance on a low-cost substrate.
- Developing high current vertical GaN power devices for up to 1200 V/100 A voltage class.
- Providing the assembly and interconnection technology for vertical GaN power switches making them as reliable as currently used power switches.
- Enabling lower cost in high power density applications (e.g. traction inverter) especially for high volume applications.
- Provide the material and equipment for future production of the here developed devices.