Periodic Reporting for period 3 - YESvGaN (Vertical GaN on Silicon: Wide Band Gap Power at Silicon Cost)
Reporting period: 2023-05-01 to 2024-10-31
For the economic as well as the ecological future of Europe energy savings and management are ground challenges. It is important to distribute and use electric energy in the most efficient manner. Thus, power transistors based on wide band gap (WBG) materials such as gallium nitride (GaN) and silicon carbide (SiC) are essential to enhance efficiency in power electronics by replacing conventional silicon (Si)-based technologies in power switches for a variety of applications and markets, such as electric vehicles, power supplies, industrial drives for e-motors or photovoltaic inverters.
However, existing lateral GaN power transistors are limited in their power handling capability while vertical SiC transistors are significantly more expensive than their Si-based counterparts. To that end, 23 European partners from research to industry joined their semiconductor and power electronics expertise in YESvGaN for an ambitious goal: to establish a new class of GaN power transistors, which combines the efficiency of WBG semiconductors with the cost benefits of Si technology. For this, innovative vertical transistor architectures using heteroepitaxial GaN layers on low-cost substrates were developed with advancements along the whole value chain, which are addressed by the following project objectives:
- Development of vertical drift epitaxy up to 1200 V blocking voltage on low-cost silicon or sapphire substrates up to 300 mm wafer size
- Development of low-cost, vertical GaN (vGaN) power transistors and process technology with performance above state-of-the-art SiC MOSFETs at chip costs competitive with Si IGBTs
- Development of membrane process technology for vGaN power transistors with ultra-low resistance contribution from the backside contact
- Development of advanced interconnection technology compatible with membrane vGaN power transistors and evaluation of their reliability based on ECPE Guideline AQG324
- Understanding performance limitations, degradation and failure mechanisms of membrane vGaN power transistors from chip to device
- Delivery of a datasheet for membrane vGaN power transistors with static and dynamic behaviour. Improvement of system efficiency by reducing losses up to 50% and by increasing power density by 15% (compared to silicon) for the chosen technology demonstrators of high-power converters in order to increase their cost efficiency.
However, existing lateral GaN power transistors are limited in their power handling capability while vertical SiC transistors are significantly more expensive than their Si-based counterparts. To that end, 23 European partners from research to industry joined their semiconductor and power electronics expertise in YESvGaN for an ambitious goal: to establish a new class of GaN power transistors, which combines the efficiency of WBG semiconductors with the cost benefits of Si technology. For this, innovative vertical transistor architectures using heteroepitaxial GaN layers on low-cost substrates were developed with advancements along the whole value chain, which are addressed by the following project objectives:
- Development of vertical drift epitaxy up to 1200 V blocking voltage on low-cost silicon or sapphire substrates up to 300 mm wafer size
- Development of low-cost, vertical GaN (vGaN) power transistors and process technology with performance above state-of-the-art SiC MOSFETs at chip costs competitive with Si IGBTs
- Development of membrane process technology for vGaN power transistors with ultra-low resistance contribution from the backside contact
- Development of advanced interconnection technology compatible with membrane vGaN power transistors and evaluation of their reliability based on ECPE Guideline AQG324
- Understanding performance limitations, degradation and failure mechanisms of membrane vGaN power transistors from chip to device
- Delivery of a datasheet for membrane vGaN power transistors with static and dynamic behaviour. Improvement of system efficiency by reducing losses up to 50% and by increasing power density by 15% (compared to silicon) for the chosen technology demonstrators of high-power converters in order to increase their cost efficiency.
Building on the results from the previous periods, individual technologies were further advanced and these results were combined to demonstrate the feasibility of the target concepts along the full value chain from epitaxial layer growth all the way to measurements in application-near test scenarios. The main activities and achievements in the 3rd period are summarized below per work package.
WP2 Epitaxy
- Increased drift layer thickness for stacks grown on silicon up to 7.4 µm and sapphire up to 10 µm. Improved doping control to increase blocking voltages up to 1200 V for GaN-on-Si and >1200V for GaN-on-sapphire. Avalanche was also found for heteroepitaxial GaN on both substrates.
- Advanced growth techniques for GaN-on-Si epitaxy with micromasking layers, leading to reduced dislocation densities of 1e8 1/cm2 with further room for improvement.
- An MOCVD reactor for 300 mm GaN-on-silicon growth was successfully installed and showed superior homogeneity for the growth of the first HEMT structures and vertical stacks.
WP3 Chip technology
- Continuous improvement of the process modules for Trench Gate MOSFETs, Planar Gate MOSFETs and FinFETs.
- Demonstration of the feasibility of running 200 mm GaN-on-Si wafers with vertical epitaxial stacks through a manufacturing line including an optimization of the source implant.
- Processing of fully vertical GaN-on-Si Trench MOSFETs with up to 16 mm2 active area.
- Demonstration of favorable channel characteristics for GaN FinFETs
- Design and assembly of a completely new 200 mm-capable ion implanter
- Detailed characterization of bias-induced capacitor and transistor instabilities and modeling thereof by TCAD simulations
WP4 Membrane processing
- Backside processing for local substrate removal of silicon end epitaxy buffer up to 200mm wafer diameter with subsequent electroplated copper metallization
- Demonstration of full substrate removal by laser lift-off of 100mm GaN-on-sapphire wafers with processed pn-diodes and verification of vertical conductivity and blocking strength of 1000 V
- Development of a backside ohmic contact process that does not need any annealing steps
WP5 AIT and reliability
- Die attach and topside wire-bond of GaN-on-Si diode and transistor chips with several techniques like soldering and advanced sintering techniques based on nanowires
- First reliability tests such as active power cycling
- First assemblies of diode chips on lead frames for molding into standardized TO-packages
- Aging tests of the joints with subsequent SEM cross section analysis
WP6 Application
- Design and fabrication of a low inductive half-bridge power module, which can integrate bare dies or discrete devices
- Testing and characterization of the power module with available SiC chips and its integration into demonstrator applications such as an inductive heater, a dual active bridge EV charger and a photovoltaic inverter.
- Characterization of vGaN transistors for their static and dynamic characteristics
- Setup of a SPICE behavioral simulation model of vGaN transistors
WP1 ‘Project Management’ and WP7 ‘Dissemination and Exploitation’ are transversal WPs organizing the work inside the project and establishing suitable communication channels to disseminate the results. YESvGaN results were disseminated via a range of conference talks, social media posts (Twitter, LinkedIn) and participation to fairs. A dedicated YESvGaN summerschool was organized which took place in August 2023 in Ghent in cooperation with two other European projects (TRANSFORM and PowerElec). Recording of summerschool lectures and other resources are available on the YESvGaN Youtube channel.
WP2 Epitaxy
- Increased drift layer thickness for stacks grown on silicon up to 7.4 µm and sapphire up to 10 µm. Improved doping control to increase blocking voltages up to 1200 V for GaN-on-Si and >1200V for GaN-on-sapphire. Avalanche was also found for heteroepitaxial GaN on both substrates.
- Advanced growth techniques for GaN-on-Si epitaxy with micromasking layers, leading to reduced dislocation densities of 1e8 1/cm2 with further room for improvement.
- An MOCVD reactor for 300 mm GaN-on-silicon growth was successfully installed and showed superior homogeneity for the growth of the first HEMT structures and vertical stacks.
WP3 Chip technology
- Continuous improvement of the process modules for Trench Gate MOSFETs, Planar Gate MOSFETs and FinFETs.
- Demonstration of the feasibility of running 200 mm GaN-on-Si wafers with vertical epitaxial stacks through a manufacturing line including an optimization of the source implant.
- Processing of fully vertical GaN-on-Si Trench MOSFETs with up to 16 mm2 active area.
- Demonstration of favorable channel characteristics for GaN FinFETs
- Design and assembly of a completely new 200 mm-capable ion implanter
- Detailed characterization of bias-induced capacitor and transistor instabilities and modeling thereof by TCAD simulations
WP4 Membrane processing
- Backside processing for local substrate removal of silicon end epitaxy buffer up to 200mm wafer diameter with subsequent electroplated copper metallization
- Demonstration of full substrate removal by laser lift-off of 100mm GaN-on-sapphire wafers with processed pn-diodes and verification of vertical conductivity and blocking strength of 1000 V
- Development of a backside ohmic contact process that does not need any annealing steps
WP5 AIT and reliability
- Die attach and topside wire-bond of GaN-on-Si diode and transistor chips with several techniques like soldering and advanced sintering techniques based on nanowires
- First reliability tests such as active power cycling
- First assemblies of diode chips on lead frames for molding into standardized TO-packages
- Aging tests of the joints with subsequent SEM cross section analysis
WP6 Application
- Design and fabrication of a low inductive half-bridge power module, which can integrate bare dies or discrete devices
- Testing and characterization of the power module with available SiC chips and its integration into demonstrator applications such as an inductive heater, a dual active bridge EV charger and a photovoltaic inverter.
- Characterization of vGaN transistors for their static and dynamic characteristics
- Setup of a SPICE behavioral simulation model of vGaN transistors
WP1 ‘Project Management’ and WP7 ‘Dissemination and Exploitation’ are transversal WPs organizing the work inside the project and establishing suitable communication channels to disseminate the results. YESvGaN results were disseminated via a range of conference talks, social media posts (Twitter, LinkedIn) and participation to fairs. A dedicated YESvGaN summerschool was organized which took place in August 2023 in Ghent in cooperation with two other European projects (TRANSFORM and PowerElec). Recording of summerschool lectures and other resources are available on the YESvGaN Youtube channel.
YESvGaN targeted the development of a new class of power transistors based on gallium nitride (GaN) for efficient and affordable power conversion. The key aspect is an innovative membrane transistor approach, which allows vertical GaN transistors to be fabricated for high voltage and high current operations as well as employing inexpensive semiconductor substrates. The final target was to provide a technology that can replace current Si-based insulated gate bipolar transistors (IGBTs) due to their comparable cost level while operating at the high efficiency of silicon carbide (SiC) field effect transistors (FETs). YESvGaN has significantly increased the maturity of the relevant technologies but more development is needed prior to a full industrialization.
YESvGaN offers the following advancements and novelties beyond the state of the art:
- Demonstration of a new vertical GaN power device architecture offering WBG performance on a low-cost substrate.
- Development of vertical GaN power devices with the final aim to reach the 1200 V voltage class and high on-state current.
- Providing the assembly and interconnection technology for vertical GaN power switches making them as reliable as currently used power switches.
- Development of a highly integrated half-bridge power module
- Providing the material and equipment for future production of the here-developed devices.
YESvGaN offers the following advancements and novelties beyond the state of the art:
- Demonstration of a new vertical GaN power device architecture offering WBG performance on a low-cost substrate.
- Development of vertical GaN power devices with the final aim to reach the 1200 V voltage class and high on-state current.
- Providing the assembly and interconnection technology for vertical GaN power switches making them as reliable as currently used power switches.
- Development of a highly integrated half-bridge power module
- Providing the material and equipment for future production of the here-developed devices.