Periodic Reporting for period 2 - ID2PPAC (Integration of processes and moDules for the 2 nm node meeting Power Performance Area and Cost requirements)
Reporting period: 2022-09-01 to 2023-08-31
In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved.
To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line.
The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025.
To continue the Moore’s law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required. The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line.
The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025.
In Lithography, ASML is integrating the first 0.55NA EUV prototypes. ZEISS SMT demonstrated a new extremely sensitive corrective surface figure tuning process hNA 0.55NA projection lens. IMS finalized the qualification process of their inline metrology. Crytur delivered YAG:Ce scintillators for EUV beam monitoring to TNO. Plansee qualified first high pressure tin storage & transport prototypes. TNO manufactured smart sample holders for EUV plasma setups and improved knowledge on degradation mechanisms of materials under EUV exposure. VDL ETG developed a new logistics concept for the wafer handler
In Metrology THERMO continued with the development of a novel e-beam scanning, CAMECA have tested a new ion source and integrated a new primary optics module on a SIMS test bench. NOVA, KLA-IL designed advanced 3D navigation algorithms and performed a preliminary feasibility test of a new camera and algorithm. AMIL developed an optical-ebeam flow for high volume manufacturing and improved Defects of Interest extraction efficiency. AMIL & Mellanox completed a data transfer benchmark activity. CRYTUR and FZU selected 3 material candidates, for AMIL’s defect review detectors. For wafer backside defects measurement, PVA built and tested first prototypes for new transducers. In the Enhanced metrology computing platform task, Mellanox emulated computing performance to AMIL’s and NOVA’s requirements and develops an SoC in line with these specifications.
Partners in the workpackage on Mask Equipment performed simulations on mask processing effects and verified a transparent coating for mask backside. A mask tuning and mask registration prototype systems have been integrated.
In Process Integration the results are: resolving 20nm pitch using single exposure interference lithography (Figure 1), completion of module build for Forksheet device (Figure 2), demonstration of 3D sequential integration for three different active layer donor wafers (Figure 3), first electrical results for Mo interconnects, down select options binary metals interconnects, completion of module build for Backside Power Delivery Network and co-integration on FinFET device wafer (Figure 4). System level assessment of Forksheet device integration options, demonstration advantages at system level of backside wafer global clock network.
In Metrology THERMO continued with the development of a novel e-beam scanning, CAMECA have tested a new ion source and integrated a new primary optics module on a SIMS test bench. NOVA, KLA-IL designed advanced 3D navigation algorithms and performed a preliminary feasibility test of a new camera and algorithm. AMIL developed an optical-ebeam flow for high volume manufacturing and improved Defects of Interest extraction efficiency. AMIL & Mellanox completed a data transfer benchmark activity. CRYTUR and FZU selected 3 material candidates, for AMIL’s defect review detectors. For wafer backside defects measurement, PVA built and tested first prototypes for new transducers. In the Enhanced metrology computing platform task, Mellanox emulated computing performance to AMIL’s and NOVA’s requirements and develops an SoC in line with these specifications.
Partners in the workpackage on Mask Equipment performed simulations on mask processing effects and verified a transparent coating for mask backside. A mask tuning and mask registration prototype systems have been integrated.
In Process Integration the results are: resolving 20nm pitch using single exposure interference lithography (Figure 1), completion of module build for Forksheet device (Figure 2), demonstration of 3D sequential integration for three different active layer donor wafers (Figure 3), first electrical results for Mo interconnects, down select options binary metals interconnects, completion of module build for Backside Power Delivery Network and co-integration on FinFET device wafer (Figure 4). System level assessment of Forksheet device integration options, demonstration advantages at system level of backside wafer global clock network.
All developments in this project are geared to move the capability of the semiconductor industry beyond the present state of the art.
The 2nm node 0.55NA EUV lithography tool represents a huge advancement beyond the state of the art as productivity will go up from 170 to 190 wafers per hour, On Product Overlay will be reduced from 2.5nm for 5nm node performance to 1.7nm for 2nm node performance and wafer and reticle particle Defectivity will be improved by a factor of 10-20. For the projection optics a 67% increase for the acceptable EUV source power limit and a reduction in surface figure deviation and OPO error contribution by 30% each, are expected. The tin storage & transport modules will need to go up in pressure by x2.5 to achieve 700 bar.
Metrology requires continuous advances beyond the state of the art. A few examples of innovative approaches in ID2PPAC are the pump-probe techniques for OCD based extraction of electrical properties, the time-domain modulated electron beam for damage free TEM microscopy of beam sensitive materials, or the use of customized electronics for very high bandwidth data transport and intelligent communication in defect inspection workflows.
State of the art Mask Equipment currently being installed can be used for production of up to 5nm node mask that will be exposed on a 0.33NA EUV tool. When the industry migrates to hNA exposure tools, significant advances in mask processing, tools and infrastructure are needed.
Process Integration achievements beyond state of the art are a forksheet device for 2nm node, i.e. performance assessment and module built, active layer transfer options for 3D sequential integration, binary metals for low resistive interconnect, BS-PDN and backside global clock network for improved power management,
The 2nm node 0.55NA EUV lithography tool represents a huge advancement beyond the state of the art as productivity will go up from 170 to 190 wafers per hour, On Product Overlay will be reduced from 2.5nm for 5nm node performance to 1.7nm for 2nm node performance and wafer and reticle particle Defectivity will be improved by a factor of 10-20. For the projection optics a 67% increase for the acceptable EUV source power limit and a reduction in surface figure deviation and OPO error contribution by 30% each, are expected. The tin storage & transport modules will need to go up in pressure by x2.5 to achieve 700 bar.
Metrology requires continuous advances beyond the state of the art. A few examples of innovative approaches in ID2PPAC are the pump-probe techniques for OCD based extraction of electrical properties, the time-domain modulated electron beam for damage free TEM microscopy of beam sensitive materials, or the use of customized electronics for very high bandwidth data transport and intelligent communication in defect inspection workflows.
State of the art Mask Equipment currently being installed can be used for production of up to 5nm node mask that will be exposed on a 0.33NA EUV tool. When the industry migrates to hNA exposure tools, significant advances in mask processing, tools and infrastructure are needed.
Process Integration achievements beyond state of the art are a forksheet device for 2nm node, i.e. performance assessment and module built, active layer transfer options for 3D sequential integration, binary metals for low resistive interconnect, BS-PDN and backside global clock network for improved power management,