In Lithography, ASML is integrating the first 0.55NA EUV prototypes. ZEISS SMT demonstrated a new extremely sensitive corrective surface figure tuning process hNA 0.55NA projection lens. IMS finalized the qualification process of their inline metrology. Crytur delivered YAG:Ce scintillators for EUV beam monitoring to TNO. Plansee qualified first high pressure tin storage & transport prototypes. TNO manufactured smart sample holders for EUV plasma setups and improved knowledge on degradation mechanisms of materials under EUV exposure. VDL ETG developed a new logistics concept for the wafer handler
In Metrology THERMO continued with the development of a novel e-beam scanning, CAMECA have tested a new ion source and integrated a new primary optics module on a SIMS test bench. NOVA, KLA-IL designed advanced 3D navigation algorithms and performed a preliminary feasibility test of a new camera and algorithm. AMIL developed an optical-ebeam flow for high volume manufacturing and improved Defects of Interest extraction efficiency. AMIL & Mellanox completed a data transfer benchmark activity. CRYTUR and FZU selected 3 material candidates, for AMIL’s defect review detectors. For wafer backside defects measurement, PVA built and tested first prototypes for new transducers. In the Enhanced metrology computing platform task, Mellanox emulated computing performance to AMIL’s and NOVA’s requirements and develops an SoC in line with these specifications.
Partners in the workpackage on Mask Equipment performed simulations on mask processing effects and verified a transparent coating for mask backside. A mask tuning and mask registration prototype systems have been integrated.
In Process Integration the results are: resolving 20nm pitch using single exposure interference lithography (Figure 1), completion of module build for Forksheet device (Figure 2), demonstration of 3D sequential integration for three different active layer donor wafers (Figure 3), first electrical results for Mo interconnects, down select options binary metals interconnects, completion of module build for Backside Power Delivery Network and co-integration on FinFET device wafer (Figure 4). System level assessment of Forksheet device integration options, demonstration advantages at system level of backside wafer global clock network.
