Periodic Reporting for period 2 - MATQu (Materials for Quantum Computing)
Période du rapport: 2022-06-01 au 2023-05-31
CMOS-based digital computing has given rise to ever-greater computational performance, big-data based business models and the accelerating digital transformation of modern economies. However, the increasingly larger amounts of data to be handled and the continuously growing complexity of today’s tasks for high performance computing (HPC) are becoming unmanageable, as data handling and energy consumption of high-performance computers, server farms and cloud services are reaching unsustainable levels. New concepts and technologies for high-performance computing (HPC) are necessary.
One such HPC technology is Quantum Computing (QC). QC utilizes “quantum bits” (qubits) to perform complex calculations fundamentally much faster than conventional digital-bit computing can. First demonstrators and quantum computer prototypes have been created using various types of quantum bits. Superconducting Josephson junctions (SJJs) have been shown to be extremely promising qubit candidates to achieve a significant, nonlinear increase of computational power with the number of qubits in a quantum computer. Industrial market-introduction of novel materials, devices, and characterization represents a great challenge yet opportunity for Europe to create a complete value chain for Josephson junction technology and QCs. Such a complete value chain will be a significant contribution to Europe’s technology sovereignty.
The MATQu project will validate technology options to produce SJJs on industrial 300 mm silicon-based process flows. The project addresses substrate technology, superconducting metals, resonator technology, through-wafer-via holes, 3D integration, and variability characterization. The substrate-, process- and test-compatibility will be assessed with respect to integration practices for qubits. Core substrate and process technologies with high quality factors, improved material deposition on large substrates, and increased critical temperature for superconducting operation, will be developed and validated.
Concerning substrate technology, process technology and tools, MATQu brings together major European actors in the field, including four large RTOs. The MATQu partners complement each other in an optimal manner across the value chain to create a substantial competitive advantage, e.g. faster time-to-market and roll-out of technologies and materials for better Josephson junctions for quantum computing.
One such HPC technology is Quantum Computing (QC). QC utilizes “quantum bits” (qubits) to perform complex calculations fundamentally much faster than conventional digital-bit computing can. First demonstrators and quantum computer prototypes have been created using various types of quantum bits. Superconducting Josephson junctions (SJJs) have been shown to be extremely promising qubit candidates to achieve a significant, nonlinear increase of computational power with the number of qubits in a quantum computer. Industrial market-introduction of novel materials, devices, and characterization represents a great challenge yet opportunity for Europe to create a complete value chain for Josephson junction technology and QCs. Such a complete value chain will be a significant contribution to Europe’s technology sovereignty.
The MATQu project will validate technology options to produce SJJs on industrial 300 mm silicon-based process flows. The project addresses substrate technology, superconducting metals, resonator technology, through-wafer-via holes, 3D integration, and variability characterization. The substrate-, process- and test-compatibility will be assessed with respect to integration practices for qubits. Core substrate and process technologies with high quality factors, improved material deposition on large substrates, and increased critical temperature for superconducting operation, will be developed and validated.
Concerning substrate technology, process technology and tools, MATQu brings together major European actors in the field, including four large RTOs. The MATQu partners complement each other in an optimal manner across the value chain to create a substantial competitive advantage, e.g. faster time-to-market and roll-out of technologies and materials for better Josephson junctions for quantum computing.
The work is carried out within 5 technical work packages (WP 1-5) and complemented by a Work Package an Communication and Dissemination (WP 6).
Activities in Work Package 1 focused on the delivery of the first set of substrate wafers, and on the design and development of the process flow for the fabrication processes of resonators on the corresponding SOI and bulk substrates.
Specific High Resistivity (HR) substrates (Silicon-on-Insulator - SOI) and bulk solutions (growth of 300mm HR silicon crystals) were prepared and delivered which are suitable for the preparation of superconducting Qubits. These were characterized (together in WP 2) and a suitable superconducting resonator design developed. The process flow of the resonators on HR SOI substrates is defined. Fabrication of resonators for electrical characterization is in process.
Suitable superconducting materials for Qubits have been screened in WP 2 and experimentally tested. Ta/Nb compounds on Si show good performance. The design of high-Q SC resonators for tests is finished and a methodology for standardized tests is available now. A baseline resonator process is available now. Thus a first step for high Q resonators which would enable 200ms relaxation time within a scalable approach has been achieve.
A fab-compatible process for the preparation of Josephson Junctions is developed. First qubit devices have been tested based on Nb resonators. A testing environment for the characterization of Josephson Junctions and resonators is under development.
Work in work package 3 concentrates on 3D integration and packaging. An ultra clean Pick & Place tool was developed by a company within the consortium. Indium was chosen as suitable superconducting solder material for microbumbs. Electroplating of In on 300mm was achieved and 2 new cleaning procedures for TSVs have been developed (accepted for publication). Several wafers have been processed for TSV preparation and testing.
In work package 4 key ingredients for qubit rapid turnaround benchmarking could be established. High-density (flexible) RF cabling based on Cri/oFlex technology were delivered to testing partners. Cryogenic testing has started including filtering and interfacing and first validation of benchmarking tests against full coaxial from 300K to mK is in progress. Cryogenic calibration and verification of I/O chain has been performed (systematic characterization of all I/O components). Reliability of all components could be improved and the variability of the components could be reduced. Cryo-CMOS multiplexers (developed outiside MATQu) are now available to the MATQu consortium.
A quantum-specific pulse/gate primitive has been fully defined in work package 5 for the simulation of time-dependent Hamiltonians. Input from experimental data to choose microscopic parameters is now awaited from characterization of hardware. The development of hardware for the effective generation of optimized pulses is in progress.
The project website has been online since June 2021. Exploitation via support of several QT initiatives has already started. 4 abstracts have been accepted for publication and 1 patent is under preparation by an industrial partner of the MATQu consortium.
Activities in Work Package 1 focused on the delivery of the first set of substrate wafers, and on the design and development of the process flow for the fabrication processes of resonators on the corresponding SOI and bulk substrates.
Specific High Resistivity (HR) substrates (Silicon-on-Insulator - SOI) and bulk solutions (growth of 300mm HR silicon crystals) were prepared and delivered which are suitable for the preparation of superconducting Qubits. These were characterized (together in WP 2) and a suitable superconducting resonator design developed. The process flow of the resonators on HR SOI substrates is defined. Fabrication of resonators for electrical characterization is in process.
Suitable superconducting materials for Qubits have been screened in WP 2 and experimentally tested. Ta/Nb compounds on Si show good performance. The design of high-Q SC resonators for tests is finished and a methodology for standardized tests is available now. A baseline resonator process is available now. Thus a first step for high Q resonators which would enable 200ms relaxation time within a scalable approach has been achieve.
A fab-compatible process for the preparation of Josephson Junctions is developed. First qubit devices have been tested based on Nb resonators. A testing environment for the characterization of Josephson Junctions and resonators is under development.
Work in work package 3 concentrates on 3D integration and packaging. An ultra clean Pick & Place tool was developed by a company within the consortium. Indium was chosen as suitable superconducting solder material for microbumbs. Electroplating of In on 300mm was achieved and 2 new cleaning procedures for TSVs have been developed (accepted for publication). Several wafers have been processed for TSV preparation and testing.
In work package 4 key ingredients for qubit rapid turnaround benchmarking could be established. High-density (flexible) RF cabling based on Cri/oFlex technology were delivered to testing partners. Cryogenic testing has started including filtering and interfacing and first validation of benchmarking tests against full coaxial from 300K to mK is in progress. Cryogenic calibration and verification of I/O chain has been performed (systematic characterization of all I/O components). Reliability of all components could be improved and the variability of the components could be reduced. Cryo-CMOS multiplexers (developed outiside MATQu) are now available to the MATQu consortium.
A quantum-specific pulse/gate primitive has been fully defined in work package 5 for the simulation of time-dependent Hamiltonians. Input from experimental data to choose microscopic parameters is now awaited from characterization of hardware. The development of hardware for the effective generation of optimized pulses is in progress.
The project website has been online since June 2021. Exploitation via support of several QT initiatives has already started. 4 abstracts have been accepted for publication and 1 patent is under preparation by an industrial partner of the MATQu consortium.
The main technical goal of the project MATQu is to improve and transfer materials and technologies for superconducting qubits from laboratories to the market. Several project partners have extensive infrastructures suited for this purpose and will contribute with their expertise in materials, process integration, and research to build robust and reproducible qubits. Industry-style fabrication infrastructures will allow optimizing process parameters and systematically improving the performance of superconducting qubits.
Complex methods to tune qubits are required to control the variability. This, in turn, adds to the complexity of quantum computer architectures compared to traditional (von Neumann) computer architectures. It is one of the main limiting factors for scaling the number of qubits in quantum computers today. MATQu aims to reduce the variability among qubit components. Researchers will investigate the impact on device variability of all material parameters and process steps. For this purpose, the consortium will gather broad knowledge and experience with developing process steps and designing experiments that allow reducing the impact of specific process parameters on device performance.
Complex methods to tune qubits are required to control the variability. This, in turn, adds to the complexity of quantum computer architectures compared to traditional (von Neumann) computer architectures. It is one of the main limiting factors for scaling the number of qubits in quantum computers today. MATQu aims to reduce the variability among qubit components. Researchers will investigate the impact on device variability of all material parameters and process steps. For this purpose, the consortium will gather broad knowledge and experience with developing process steps and designing experiments that allow reducing the impact of specific process parameters on device performance.