Project description
Stacked 2D materials offer the potential for low-power electronics
Continuous progress in semiconductor technology has led to the development of faster and smaller transistors. The metal-oxide semiconductor field-effect transistor (MOSFET) is the most widely used FET. However, a major limitation is its low power efficiency, which is attributed to its large operating voltage and the inability to limit the off-state leakage current. The tunnel FET, an experimental type of transistor, can overcome this limitation by leveraging quantum mechanical tunnelling. The EU-funded 2D-LOTTO project will address key challenges that limit the realisation of high-performance tunnel FETs. The integration of low-resistance p- and n-type contacts, negative capacitance materials and 2D vertical semiconductor heterostructures with ideal interfaces should provide ultra-low power, CMOS-compatible tunnel FETs that could transform IoT, Big Data and computing.
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Funding Scheme
ERC-ADG - Advanced GrantHost institution
CB2 1TN Cambridge
United Kingdom