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Engineering low power tunnel transistors based on two-dimensional semiconductors

Project description

Stacked 2D materials offer the potential for low-power electronics

Continuous progress in semiconductor technology has led to the development of faster and smaller transistors. The metal-oxide semiconductor field-effect transistor (MOSFET) is the most widely used FET. However, a major limitation is its low power efficiency, which is attributed to its large operating voltage and the inability to limit the off-state leakage current. The tunnel FET, an experimental type of transistor, can overcome this limitation by leveraging quantum mechanical tunnelling. The EU-funded 2D-LOTTO project will address key challenges that limit the realisation of high-performance tunnel FETs. The integration of low-resistance p- and n-type contacts, negative capacitance materials and 2D vertical semiconductor heterostructures with ideal interfaces should provide ultra-low power, CMOS-compatible tunnel FETs that could transform IoT, Big Data and computing.

Objective

Modern electronics consume a huge amount of world’s energy – currently ~ 5% and rising to > 20% in 2030. Field effect transistors (FETs) account for a large fraction of the energy consumed in electronics due to high OFF state (leakage) currents and large operating voltage (~ 0.8V). Tunnel FETs (TFETs) based on two-dimensional semiconductors (2D SCs) provide unique and game-changing solutions for both of these problems and can be engineered using industry compatible complementary metal oxide semiconductor (CMOS) processes. However, despite the intense effort over the past decade, serious challenges remain in realizing high performance TFETs. The challenges, related to achieving high quality p- and n-type contacts, practical ON state currents and scalability, arise from the lack of precise control of material interfaces. Therefore, completely new approaches in materials and process engineering are needed to reap the benefits of 2D SCs for TFETs. 2D-LOTTO provides these frontier approaches to TFET challenges by designing and engineering vertical heterostructures of 2D SCs with novel ultra-clean, low resistance p- and n-type near ideal van der Waals (vdW) contacts that allow operation at ~ 100 mV. Internal electric field amplification to boost ON state currents to practical levels will be achieved for the first time by using negative capacitance (NC) gate dielectrics. The integration of vdW contacts, NC gates and 2D SC heterostructures with ideal interfaces will provide ultra-low power, CMOS compatible TFETs that have the potential to transform the technology landscape in IoT, Big Data and computing. Initially, automated mechanical exfoliation of 2D SC vertical heterostructures will be used to design and test TFETs. Then, CMOS compatible metal organic chemical vapor deposition (MOCVD) will be used to realize wafer scale devices. The viability of proposed approach is confirmed by proof of concept demonstrations reported by the PI in engineering 2D SCs for FETs.

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Coordinator

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Net EU contribution
€ 2 499 948,00
Address
Trinity lane the old schools
CB2 1TN Cambridge
United Kingdom

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Region
East of England East Anglia Cambridgeshire CC
Activity type
Higher or Secondary Education Establishments
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Other funding
€ 0,00

Beneficiaries (1)