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Engineering low power tunnel transistors based on two-dimensional semiconductors

Project description

Stacked 2D materials offer the potential for low-power electronics

Continuous progress in semiconductor technology has led to the development of faster and smaller transistors. The metal-oxide semiconductor field-effect transistor (MOSFET) is the most widely used FET. However, a major limitation is its low power efficiency, which is attributed to its large operating voltage and the inability to limit the off-state leakage current. The tunnel FET, an experimental type of transistor, can overcome this limitation by leveraging quantum mechanical tunnelling. The EU-funded 2D-LOTTO project will address key challenges that limit the realisation of high-performance tunnel FETs. The integration of low-resistance p- and n-type contacts, negative capacitance materials and 2D vertical semiconductor heterostructures with ideal interfaces should provide ultra-low power, CMOS-compatible tunnel FETs that could transform IoT, Big Data and computing.

Host institution

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Net EU contribution
€ 2 499 948,00
Address
Trinity Lane The Old Schools
CB2 1TN Cambridge
United Kingdom

See on map

Region
East of England East Anglia Cambridgeshire CC
Activity type
Higher or Secondary Education Establishments
Non-EU contribution
€ 0,00

Beneficiaries (1)

THE CHANCELLOR MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
United Kingdom
Net EU contribution
€ 2 499 948,00
Address
Trinity Lane The Old Schools
CB2 1TN Cambridge

See on map

Region
East of England East Anglia Cambridgeshire CC
Activity type
Higher or Secondary Education Establishments
Non-EU contribution
€ 0,00