Periodic Reporting for period 2 - AnalogCreate (Autonomous Creation of Analog Integrated Circuits based on Self-Learning of Design Expertise)
Reporting period: 2023-03-01 to 2024-08-31
Progress in semiconductor technology and in intelligent data processing are converging today, opening the door to countless smart ICT applications through the Cloud and Internet of Everything, to the people’s benefit in years to come. Applications that interact with the physical world (e.g. environmental sensing, healthcare, autonomous vehicles, etc.), also need analog integrated circuits in the cyber-physical or edge layer. But while digital circuits are largely synthesized automatically through software, the analog circuits are mainly still handcrafted in industry with low design productivity. This results in long and error-prone design cycles, and the high development costs jeopardize many potential new ICT applications from ever being realized (e.g. solutions for rare diseases). It becomes even more problematic when moving to advanced technologies below 16 nm CMOS, that come with way more design and layout rules to be dealt with. The showstopper for state-of-the-art analog synthesis tools is that they require design heuristics and constraints to be entered explicitly by designers in order to handle the humongous solution space and to steer the circuit and layout optimizations towards acceptable solutions.
The AnalogCreate project aims at increasing the design productivity of analog circuits by at least two orders of magnitude (100x) compared to the current practice, while improving the design optimality and the design correctness. The proposed disruptively new approach is to use the self-learning capabilities of advanced machine learning algorithms to self-learn and then exploit the design expertise and constraints from the many available designs successfully completed by experts. Also a true circuit topology synthesis approach will be developed to create a proper (possibly novel) schematic from the target specifications, as well as an innovative formal analog design verification and test validation approaches. These innovations aim for the first time ever to truly autonomously create analog circuits from specifications to fully verified layout without direct input from any designer in the loop, and therefore enable the affordable implementation of many promising ICT applications.
The AnalogCreate project aims at increasing the design productivity of analog circuits by at least two orders of magnitude (100x) compared to the current practice, while improving the design optimality and the design correctness. The proposed disruptively new approach is to use the self-learning capabilities of advanced machine learning algorithms to self-learn and then exploit the design expertise and constraints from the many available designs successfully completed by experts. Also a true circuit topology synthesis approach will be developed to create a proper (possibly novel) schematic from the target specifications, as well as an innovative formal analog design verification and test validation approaches. These innovations aim for the first time ever to truly autonomously create analog circuits from specifications to fully verified layout without direct input from any designer in the loop, and therefore enable the affordable implementation of many promising ICT applications.
The AnalogCreate project aims at increasing the design productivity of analog circuits by at least two orders of magnitude (100x) compared to the current practice, while improving the design optimality and the design correctness. A major innovation is to use the self-learning capabilities of advanced machine learning algorithms to self-learn the design expertise and constraints from available designs successfully completed by experts, to then apply this to the synthesis of new circuits with no expert being in the loop any further. The overall methodology and initial findings have been presented by Gielen at the MPSoC’22 and ASP-DAC'23 conferences as well as in a keynote presentation at the MLCAD 2023 conference. In addition, significant technical progress has been made in the different research lines of the project, also resulting in the first publications at top international conferences and journals. The work on analog circuit sizing optimization is based on model-boosted (hierarchical) reinforcement learning and will be published at the DAC 2024 conference. The work on analog layout synthesis is based on the self-learning of geometric constraints from existing layouts, following by transfer learning these to new layouts, and has been published at the recent DATE 2024 conference. Finally, the verification work has focused on machine-learning-based post-fabrication validation to detect the presence of latent defects in the circuits from the traditional testing data. This work has been published in the IEEE Transactions on Computer-Aided Design.
The project has increased the efficiency of analog circuit sizing optimization and analog layout synthesis with several factors compared to the current state of the art. In addition, the detection coverage of latent defects in mixed-signal ICs has been boosted enormously with little or no overhead cost. While these are already great achievements, to achieve the very ambitious project targets, additional algorithmic improvements will be needed in the second period of the project.